Oasys RealTime Explorer Bridges Logical and Physical IP for Improved QoR
Santa Clara, CA January 29, 2013 Oasys Design Systems announced today that it has joined the TSMC Soft-IP Alliance Program to enable TSMC IP partners with a new RTL exploration tool to improve quality of results and reduce the iterations required for design closure. RTL engineers implementing complex IP cores for graphics, networking, and mobile computing are struggling with new QoR and time to market issues. The introduction of RealTime Explorer by Oasys enables RTL engineers to have a physically aware, implementation accurate synthesis tool for top-level PPA and routing analysis without requiring them to be physical design experts.
The TSMC Soft IP Alliance program is an extension of TSMCs IP Alliance program that allows Soft-IP partners to access and leverage TSMCs advanced process technologies to optimize power, performance, and area for their IP. TSMC offers a large catalog of ecosystem-partner and RTL-based Soft-IP. Provider cores are checked through the TSMC foundry checklist to ensure the best possible design experience, easiest design reuse, and the fastest integration into the overall design system.
The complexity and size of todays soft IP blocks have created huge bottlenecks in synthesis runtimes sometimes requiring many days to check the result of a single change to the RTL , said Paul van Besouw, Oasys founder and CTO. Further, RTL engineers moving to 28nm nodes and beyond have struggled because of the lack of physical awareness within their traditional synthesis tools. The Oasys RealTime engine optimizes at a higher level of abstraction, allowing RTL engineers to change and check their RTL in hours not days.
We welcome the new RTL exploration capability provided by Oasys Design addressing IP complexity, said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. The logical-to-physical cross probing capability that promises quick analysis of the root cause of timing and routing issues before handoff for physical design could have a profound time-to-market impact for our IP partners.
About Oasys Design Systems
Oasys Design Systems is a privately funded electronic design automation (EDA) software supplier with a revolutionary new synthesis platform called RealTime, a fundamental shift in how RTL synthesis is used to design and implement todays SoCs and ASICs. Corporate headquarters is located at 3250 Olcott Street, Suite 105, Santa Clara, Calif. 95054. Telephone: (408) 855-8531. Facsimile: (408) 855-8537. Email: firstname.lastname@example.org. For more information, visit: www.oasys-ds.com.