Imec and Target present multi-standard low-power LDPC engine for multi-Gbps wireless communication

Imec and Target consolidate collaboration to advance ASIP design, reducing the cost, performance and power consumption of mobile systems-on-chip

Barcelona (Spain), February 25, 2013. At the Mobile World Congress, imec and Target Compiler Technologies announced that they extend their strategic collaboration on ASIP (application-specific instruction-set processor) designs in the field of mobile communication. One of the achievements endorsing their fruitful collaboration in the past years is a new multi-standard LDPC (low-density parity check) FEC (forward error correction) ASIP architecture template for multi-Gbps wireless communication. This programmable LDPC engine is compliant with different standards such as 802.11ad (60GHz) and 802.11ac, and outperforms dedicated hard-wired implementations in throughput and energy efficiency.

“A strong ASIP design flow is critical to gain a competitive engineering advantage in cost, performance and power of reconfigurable radio architectures,” said Liesbet Van der Perre, Green Radio program director at imec. “Target Compiler Technologies offers a very compelling technology in this area.  We are pleased to extend our licensing and R&D partnership with them, and we are looking forward to jointly develop new breakthroughs in digital architectures for next-generation mobile applications and technologies.”

Using Target’s IP Designer™ tool-suite for the design and programming of ASIPs, imec designed a multi-Gbps LDPC processor template that uses a programmable datapath architecture with parallel slices supporting instruction and data-level parallelism.  The locality of reference imposed by the slices concept results in high energy efficiencies. The ASIP was validated for the 802.11ad (60GHz) standard in a commercial 40nm technology.  Surpassing power, area and throughput of known dedicated fixed-function implementations, the multi-standard layered LDPC decoding engine achieved a throughput up to 7.6 Gbps at 3 iterations with a latency of less than 90 ns and a record energy efficiency of 4 pJ/bit/iteration in 40G TSMC technology. Moreover, owing to the instantaneous availability of an efficient software development environment, the ASIP methodology offers high productivity and easy instantiation to other multi-Gbps modes and standards like 802.11ac.

Gert Goossens, Target’s CEO, said: “The implementation by imec of this new flexible FEC architecture based on our IP Designer tool-suite proves that programmable ASIP solutions can compete with fixed-function hardwired IP blocks for advanced wireless standards, delivering superior performance results. IP Designer allows to quickly validate the impact of architectural changes on throughput, latency, silicon area and power consumption, thereby reducing the design risk. Additionally, ASIP implementations resolve issues with the instability of emerging standards and enable system-on-chip customers to include proprietary features in their chipsets. In recent years, Target Compiler’s IP Designer has been adopted by major industrial players to design their wireless modem solutions."

About imec

Imec performs world-leading research in nanoelectronics. Imec leverages its scientific knowledge with the innovative power of its global partnerships in ICT, healthcare and energy. Imec delivers industry-relevant technology solutions. In a unique high-tech environment, its international top talent is committed to providing the building blocks for a better life in a sustainable society. Imec is headquartered in Leuven, Belgium, and has offices in Belgium, the Netherlands, Taiwan, US, China, India and Japan. Its staff of close to 2,000 people includes more than 600 industrial residents and guest researchers. In 2011, imec's revenue (P&L) was about 300 million euro. Further information on imec can be found at www.imec.be.

About Target Compiler Technologies

Target Compiler Technologies offers software tools to system and semiconductor companies for the design of advanced multicore systems-on-chip (SoCs).  Target’s IP Designer™ product is the leading tool-suite that enables and accelerates the design, programming and verification of application-specific processor cores (ASIPs). Target’s MP Designer™ product is a tool-suite for software parallelization on multicore SoC architectures. These tools are ideally suited for SoC designs in markets that mandate low silicon cost, low energy consumption, and flexibility to accommodate algorithmic changes. Target’s tools have been used by customers around the globe to design SoCs for 2G/3G/4G handsets, cordless and VoIP phones, audio/video/image processing, infotainment and security for cars, DSL modems, DSL access multiplexers, wireless LAN, hearing instruments, and personal healthcare systems. Target is a spin-off of imec, is headquartered in Leuven, Belgium, with North American operations in Boulder, Colorado.  For more information, visit www.retarget.com.