Barcelona, Spain -- February 27, 2013: VLSI Plus, a leading provider of MIPI CSI2 complaint IP cores, today announced at the MWC conference the availability of the SVT-CS4-AP2 â a MIPIÂ® CSI2 compliant serial video transmitter, supporting multiple concurrent video sources, and employing from 1 to 4 DPHY lanes at up to 1.5Gbps per lane.
This product, complementing the veteran SVT-CS4-AP1, which supports a single video source, is initially offered in ASIC version, to be followed by an FPGA version in Q2 2013.
VLSI Plus (www.vlsiplus.com) is a boutique IP house, specializing in digital video and, in particular, in IP cores complying with MIPIÂ® CSI2 and CSI3 Camera Serial Interface standard. VLSI Plus is the first CSI2 IP core vendor to get MIPIÂ® IOL certificate.
Yoav Lavi, founder and CEO of VLSI Plus said: âWith this feature, the customer can make full use of the CSI2 flexibility. For example, the IP may concurrently transmit a high resolution RAW12 format, where the first and last video lines carry blanking data and have a different data type, segments of JPEG thumbnail and low-resolution high frame-rate view-finder image. The various video sources may have different data types, video height and width, virtual channel number and pixel clock rates.â