Grenoble, France – March 04, 2013. Dolphin Integration invites users of the TSMC 55 LP process to try out the latest Foundry Sponsored SpRAM released, known as SpRAM RHEA generator. This SpRAM is designed to reach the highest density and gains from 7% to 20% versus alternative solutions, depending on the memory configuration required.
The SpRAM RHEA has now passed the pre-silicon assessment criteria (Level 1) of TSMC’s stringent IP9000 qualification program.
Example of benchmark results for 8kx32 memory cut
Dolphin Integration's SpRAM RHEA not only provides the best density but also includes a data retention mode. To achieve the lowest leakage, the data retention mode supports a voltage as low as 0.77 V. This minimum voltage retention feature enables to divide leakage by 4 compared to alternative memory generators in stand-by mode.
The SpRAM RHEA operates as fast as 350 MHz in worst-case conditions in the LP process to satisfy at once the need for increased computing power without sacrificing power consumption and density.
For more information about this product, feel free to download the Presentation Sheet or to contact Dolphin’s Library Marketing Manager at email@example.com
To request an access to the FE generator for evaluation purpose or to the BE generator for integration, please request an access.
Dolphin Integration broad library portfolio for 55 nm LP includes logic silicon IPs with the SESAME standard cell libraries and their all-encompassing kit for islet construction, and also Single Port and Dual Port RAM generators, via programmable ROM generator, and their power Regulators bundled in complete Panoplies.
About Dolphin Integration
Dolphin Integration contribute to "enabling mixed signal Systems-on-Chip". Their focus is to supply worldwide customers with fault-free, high-yield and reliable kits of CMOS Virtual Components of Silicon IP, based on innovative libraries of standard cells, flexible registers and low-power memories. They provide high-resolution converters for audio and measurement, regulators for efficient power supply networks, application optimized micro-controllers.
They put emphasis on resilience to noise and drastic reductions of power-consumption at system level, thanks to their own EDA solutions missing on the market for Application Hardware Modeling as well as early Power and Noise assessment. Such diverse experience in ASIC/SoC design and fabrication, plus privileged foundry portal even for small or medium volumes, makes them a genuine one-stop shop covering all customers’ needs for specific requests.