EverOn Ultra Low Voltage Embedded SRAM TSMC 40ULP Embedded Flash
Real Intent brings clock checking to formal tool
Real Intent brings clock checking to formal tool
By Michael Santarini, EE Times
May 29, 2002 (6:10 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020528S0046
SANTA CLARA, Calif. Real Intent Corp. has added what it terms formal clock intent verification to its Verix assertion-driven formal verification tool.
The feature breaks new ground because it analyzes and verifies the stability and correctness of data transfer between clock domains, said Prakash Narain, president and chief executive officer of Real Intent, based here.
"Today's SoCs and communication designs commonly have multiple clock domains, which means different parts of the design are being clocked at different rates," Narain said. "To ensure reliable data path across these interfaces, designers have to employ guidelines that have to do with structural as well as logical design."
He said that the feature, which will be available in version 4.0 of Verix this summer, ensures that the structural and logical guidelines are followed.
Narain explained how it works: Users feed the tool RTL code, either Verilog or V HDL, and identify clocks and resets in their design. Then, the tool automatically identifies the clock domains and the hazards for signals crossing those domains. The absence or presence of synchronizers at the clock domain boundaries also are identified. After running the analysis, the feature advises designers about what assertions they need to place into their designs to formally verify that the data transfer is implemented effectively.
Version 4.0 with the assertion-based formal clock intent verification is being used successfully at beta customer sites, Narain said.
Version 4.0 is also expected to include full-functional VHDL support. Pricing starts at $50,000 per year.
Related News
- Real Intent Announces Verix Multimode DFT Static Sign-Off Tool
- Real Intent Delivers Major Innovation in Clock Domain Crossing Sign-off of SoC Designs
- Real Intent and Calypto Partner to Offer Best-in-Class Integrated Tool Flow for RTL Power Optimization and Sign-Off
- Real Intent Introduces Meridian FPGA, Popular Clock Domain Crossing Verification Software for Altera Customers
- Real Intent Introduces Conquest(TM) and Ascent(TM), Leading the New EnVision(TM) High-Performance Formal Verification Family
Breaking News
- Synopsys Showcases EDA Performance and Next-Gen Capabilities with NVIDIA Accelerated Computing, Generative AI and Omniverse
- Spectral Releases Advanced Quality Assurance & Data Analytics tool to validate advanced node Memory Compilers
- TSMC and Synopsys Bring Breakthrough NVIDIA Computational Lithography Platform to Production
- After TSMC fab in Japan, advanced packaging facility is next
- A System On Module (SoM) developed by Electra IC: BitFlex-SPB-A7 FPGA SoM
Most Popular
- After TSMC fab in Japan, advanced packaging facility is next
- HBM3 Initially Exclusively Supplied by SK Hynix, Samsung Rallies Fast After AMD Validation, Says TrendForce
- Alphawave Semi Demonstrates 3nm Silicon-Proven 24Gbps Universal Chiplet Express (UCIe) Subsystem for High-Performance AI Infrastructure
- Weebit Nano to demo its ReRAM technology on GlobalFoundries' 22FDX® platform
- We'll Need Many More Fabs to Meet $1 Trillion by 2030 Goal
E-mail This Article | Printer-Friendly Page |