Standards include LPDDR4, Wide I/O 2, eMMC 5.0, HMC and DDR4 LRDIMM
SAN JOSE, Calif., 06 Aug 2013 -- At MemCon 2013 today, Cadence Design Systems, Inc. (NASDAQ: CDNS), announced the immediate availability of new verification IP (VIP) models for the latest memory standards--LPDDR4, Wide I/O 2, eMMC 5.0, HMC and DDR4 LRDIMM.
Advanced features of these new models include trace debug, address scrambling and backdoor memory access. Additionally, the models support all leading third party simulators, verification languages and methodologies, enabling SoC designers to verify the correctness of interfaces to these new, specialized memories.
Memory is playing an important role in the increased functionality and performance of mobile devices such as smartphones and tablets, said Mian Quddus, chairman of the JEDEC Board of Directors. LPDDR4 and Wide I/O 2 are key new standards for memory interfaces, and the availability of memory models will allow designers to take advantage of these standards quickly.
Theres a new dynamic today in which designers are faced with more standards being introduced but with shorter lifecycles. At the same time, they need to address power, performance, cost, thermal and packaging constraints, said Martin Lund, senior vice president of Cadences IP Group. To address this, we are providing access to models supporting as many standards options as possible, so designers can get to market success as fast as possible.
Cadence enables global electronic design innovation and plays an essential role in the creation of todays integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.