Nick Flaherty, Embedded Editor, EE Times Europe
10/15/2013 12:15 PM EDT
One of the fascinating things about yesterday's launch of the newest MIPS core is not the core itself. We've argued about the details of Release 5 of the MIP instruction set architecture for nearly a year now, so the microarchitecture of the first Warrior device is no real surprise.
What is very interesting is the support block that actually makes it usable in an SoC device, and this has obviously had a lot of attention paid to it.
The coherence manager combines six CPU cores with the L2 cache and I/O managers. These maintain the coherency and are a key support for the hardware virtualization. But 6 is a strange number in this binary world.
Click here to read more ...