0-In Demonstrates the Value of Assertion-Based Verification (ABV) throughout the Design Cycle at the Design Automation Conference

Come see how 12 of the world's 15 largest electronics companies are using 0-In's ABV methodology to

• Increase Tapeout Confidence
• Find Bugs Missed in Simulation
• Ensure Thorough Verification
• Reduce Time to Market

SAN JOSE, Calif. - June 4, 2002 - 0-In Design Automation, Inc., The Assertion-Based Verification Company, will present its complete Assertion-Based Verification (ABV) solution at the Design Automation Conference (DAC) from June 9-13 in New Orleans. 0-In invites those interested in a demonstration of its latest products or a discussion of its ABV methodology to visit Booth #3152 at DAC or to request a private suite demonstration at http://www.0-in.com/misc/dac_demo_form.php. An overview presentation of 0-In's ABV solutions can be found at http://www.0-in.com.

Assertion-Based Verification enables designers to capture design intent in the form of assertions and validate these assertions using simulation and formal verification technology at all levels of abstraction from the block to the system level. Companies are increasingly turning to ABV to reduce their verification time and improve their verification thoroughness.

"Seventy percent of development effort is spent on functional verification, which clearly indicates that traditional simulation methods are inadequate," said Emil Girczyc, 0-In president and CEO. "Our customers have found that Assertion-Based Verification not only reduces their verification effort, but also finds bugs missed by classical directed and pseudo-random simulation. 0-In provides the only complete ABV solution across simulation, formal verification, emulation and rapid prototyping platforms."

At DAC, 0-In will demonstrate its current products and will also preview its next-generation assertion-based verification technologies, designed to further supercharge verification flows. Products to be demonstrated include:

• 0-In Check, a comprehensive assertion management system that improves observability during simulation and grades testbench efficacy with structural coverage metrics.
• 0-In Search, a dynamic formal verification tool, which increases tapeout confidence by performing an exhaustive analysis of designer-specified assertions.
• 0-In CheckerWare® Library and Monitors, a rich library of Verification IP, which makes it easy to specify re-usable complex assertions. This library of assertion checkers is validated with static and dynamic formal technologies. Available Verification IP includes over 20 CheckerWare® Monitors for industry-standard protocols such as Infiniband, AGP, AMBA, PCI, PCI-X POS-PHY, UTOPIA, CSIX, SPI-4, HyperTransport, SDRAM, SRAM, and DDR SDRAM.

Customer Success Highlights:
0-In will present customer experiences using its established ABV solutions to reduce the verification time of complex designs. 0-In's customers span a wide range of product applications - microprocessor, chipset, server, multimedia, telecommunications, networking and IP cores - in design centers throughout Europe, Asia and North America.

Conference Technical Program:
Curt Widdoes, chairman and CTO of 0-In and an industry expert in verification technologies, will be on the panel "Formal Verification Methods: Getting Around the Brick Wall" discussing how to overcome the barriers to adopting formal verification on Thursday, June 13, 8:30-10:00 am in Auditorium A.

About 0-In
About 0-In About 0-In 0-In Design Automation, Inc. (pronounced "zero-in") develops and supports functional verification products that help verify multi-million gate application-specific integrated circuit (ASIC) and system-on-chip (SoC) designs. Twelve of the fifteen largest electronics companies worldwide have adopted 0-In tools and methodologies in their integrated circuit (IC) design verification flows. 0-In was founded in 1996 and is based in San Jose, Calif. For more information, see http://www.0-in.com.

0-In® and CheckerWare® are trademarks of 0-In Design Automation, Inc.
 
 

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