Chartered signs deal with analog IP house Unive for SoC designs
Chartered signs deal with analog IP house Unive for SoC designs
By Semiconductor Business News
June 10, 2002 (5:27 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020610S0074
SINGAPORE -- Singapore's Chartered Semiconductor Manufacturing Pte. Ltd. today announced an agreement with analog IC intellectual property (IP) provider Unive Inc.--a move that would enable mixed-signal system-on-a-chip (SoC) designs. The non-exclusive agreement between the two companies initially covers Unive's LVDS, SSTL2 and USB 2.0 IP offerings targeted for devices using Chartered's 0.18-micron and 0.13-micron processes. It also provides the option to expand into other Unive IP offerings and Chartered manufacturing products, including 90-nm technologies. Companies pay an upfront fee and no royalties for design-in access. The Unive LVDS, SSTL2 and USB2.0 offerings are expected to be available for Chartered's 0.18-micron and 0.13-micron processes in the third quarter of 2002, according to Milpitas, Calif.-based Unive.
Related News
- Open-Silicon Integrates 25 Analog Bits IP Cores Into Complex ASIC and SoC Designs
- ARM, Chartered, IBM, Samsung, and Synopsys Collaborate to Deliver Vertically Optimized Solution for 32/28nm Mobile SoC Designs
- True Circuits Features New Line of 65nm PLL & DLL Intellectual Property for ASIC, FPGA and SoC Designs at Chartered Technology Forum 2006 - USA
- Microchip FPGAs Speed Intelligent Edge Designs and Reduce Development Cost and Risk with Tailored PolarFire® FPGA and SoC Solution Stacks
- Synopsys and TSMC Collaborate to Accelerate 2nm Innovation for Advanced SoC Design with Certified Digital and Analog Design Flows
Breaking News
- PUFsecurity Unveils Next-Gen Crypto Coprocessor PUFcc7 Featuring High-speed Performance and TLS 1.3 Support
- VeriSilicon's complete Bluetooth Low Energy IP solution is fully compliant with LE Audio specification
- TASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP
- Efabless Launches an "AI Wake Up Call" Open-Source Silicon Design Challenge
- Efinix Rolls Out Line of FPGAs to Accelerate and Adapt Automotive Designs and Applications
Most Popular
- Qualitas Semiconductor and Ambarella Sign Licensing Agreement
- ZeroPoint Technologies Signs Global Customer to Bring Hardware-Accelerated Compression to Hyperscale Data Centers
- Chiplet Interconnect Pioneer Eliyan Closes $60 Million Series B Funding Round, Co-led by Samsung Catalyst Fund and Tiger Global Management to Address Most Pressing Challenge in Development of Generative AI Chips
- Intel and Arm Team Up to Power Startups
- Alphawave Semi and InnoLight Collaborate to Demonstrate Low Latency Linear Pluggable Optics with PCIe 6.0® Subsystem Solution for High-Performance AI Infrastructure at OFC 2024
E-mail This Article | Printer-Friendly Page |