Memoir Systems offers TSMC customers ultra-high performance multiport memories built on Memoir’s IP delivery platform enabling first-time-silicon success
SANTA CLARA, Calif., January 13, 2014—Memoir Systems Inc., today announced that it has joined the TSMC Soft IP Alliance Program, leveraging TSMC’s advanced process technologies to improve power, performance and area for its Renaissance family of multiport memory IP. Using Memoir’s IP delivery platform that includes design-for-formal and exhaustive formal verification, Memoir delivered fully verified ultra-high performance multiport memory IPs to TSMC. The TSMC Soft IP Alliance Program requires rigorous checks and quantitative data to demonstrate the robustness and completeness of synthesizable semiconductor IP that is part of the TSMC 9000 IP library. These IPs successfully passed TSMC’s comprehensive soft IP qualification process ensuring the best possible design experience, easiest design reuse and the fastest integration into SOCs.
New SOCs are constructed predominately by assembling a multitude of IP building blocks, with as many as 50-80% of those being memory. Therefore, the quality of IP building blocks and the ease with which they can be integrated for a particular process has a huge impact on time to market and customer success.
“Our IP delivery platform rapidly provides formally proven synthesizable memories of various address and multiport combinations, thus alleviating the need for test chip qualification and enabling first-time-silicon success,” said Sundar Iyer, co-founder and CEO at Memoir. “As the leading merchant foundry, our customers depend on TSMC. Now all TSMC customers will have access to our versatile multiport memory IP that is easy to integrate and offers breakthrough performance, and industry leading area and power efficiency.”
In many SOCs, embedded memory performance is the limiting factor. As the processor-embedded memory gap widens, higher performance multiport memories are required to unlock application potential. Memoir’s Renaissance memories combine single port embedded memory macros with sophisticated algorithms to increase memory performance by up to 10X. The algorithms are implemented in standard RTL logic and expose multiple memory interfaces that allow multiple parallel accesses within a single memory clock cycle. The resulting multiport memory is delivered as soft IP. It is fully verified to cover all corner cases, and offers guaranteed performance for fully random and non-random memory accesses, while reducing area and power consumption.
"Memoir’s synthesizable memories and strong focus on IP quality are a natural fit for TSMC’s Soft IP Alliance Program,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. “We welcome Memoir to the program and are pleased that their multiport memory IP will be available to TSMC customers for their next SOC designs."