Synopsys Donates Key Verification Technologies to Accellera's SystemVerilog 3.1 Standard

Synopsys Support of SystemVerilog Accelerates Evolution of Higher-Level Verification Standards

MOUNTAIN VIEW, Calif., June 11, 2002 - Synopsys, Inc. (Nasdaq: SNPS), the technology leader for complex integrated circuit (IC) design, today announced its support for SystemVerilog 3.0 and donation of several technologies to Accellera for SystemVerilog version 3.1. Accellera drives electronic design automation (EDA) standards, which enhance a language-based design automation process. The donations include testbench modeling capabilities, OpenVera™ assertions, a C/C++ model interface and a coverage application programming interface (API) that provides links to coverage metrics.

"Accellera welcomes Synopsys' donation and is thrilled with their involvement in Accellera's standardization process," said Vassilios Gerousis, technical coordinating committee chair at Accellera. "When leading EDA companies make strong technical donations to SystemVerilog, they not only make the language more robust, they support interoperable standards that allow the best EDA tools and methodologies to work seamlessly together. Synopsys was instrumental in making Verilog the de facto standard for RTL design. We look forward to working with Synopsys to lead the effort to do the same with SystemVerilog."

"Synopsys has been active in promoting standards through their numerous interoperability efforts and they've been a long standing contributor to Accellera's efforts," noted Dennis Brophy, chairman of Accellera. "Synopsys continues to demonstrate their commitment to standards with their donations to Accellera's SystemVerilog, which will help unify our assertions standard and create the next generation of the hardware description languages."

Synopsys is making four key donations to SystemVerilog 3.1. OpenVera testbench constructs help engineers quickly and easily develop testbenches within the Verilog language. These testbench constructs include: dynamic objects such as classes; built-in testbench primitives like mailboxes; and advanced control constructs such as fork-joins and triggers. The donated OpenVera assertions enable users to write protocol checkers for dynamic simulation and properties for register transfer level (RTL) formal analysis. This facilitates the emerging assertion-based verification methodology. The C/C++ model interface makes it easier to link C/C++ models or modules directly into a Verilog simulation. This enables a more efficient simulation when the full visibility of the Verilog API is not necessary. The coverage API defines a procedural interface that lets users and EDA tool developers have a consistent method of accessing coverage metrics.

"Synopsys provides the backbone of our verification flow, and we rely on their continued technology innovation," said Chris Malachowsky, vice president of engineering at NVIDIA. "Support within Synopsys products for SystemVerilog 3.0 will create a major productivity leap for designers at NVIDIA."

"Advancing the Verilog standard with inclusion of key proven technology is critical to Intel to continue to increase the productivity of our designers," said Greg Spirakis, vice president of Design Technology at Intel. "Unifying assertions in SystemVerilog will allow us to leverage advanced third party EDA tools that support the new SystemVerilog version."

"Sun is a long time champion of open standards and was involved in the development of the Vera language. The Vera language and related Synopsys verification tools are used by Sun in the development of advanced microprocessors," said Shrenik Mehta, senior engineering manager, Global Testability, Tools and Validation, Processor Products Group, Sun Microsystems, Inc. "We are pleased at the prospect of these key proven technologies becoming a part of the SystemVerilog standard from Accellera."

"There are many paths to interoperability, including working with formal standards organizations and creating standards within open source communities. We recognize Accellera as the most effective formal standards organization in EDA and as the definitive body for enhancing Verilog through to the IEEE," said Rich Goldman, vice president of strategic market development at Synopsys. "Over the years, Accellera has delivered many mission critical standards that are used by Synopsys and its customers. We are proactively working with Accellera to ensure that our customers continue to have the best standards incorporating proven technologies."

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS), headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com/.

Synopsys is a registered trademark of Synopsys, Inc. OpenVera is a trademark of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.