Grenoble, France -- February 10, 2014 -- The high density and low power architecture RHEA for SpRAM is now available in the eFlash process variant for the 90 nm and 55 nm nodes.
This SpRAM is designed to reach the highest density and gains from 10 to 20% versus alternative solutions in 90 nm and 55 nm.
Dolphin Integration's RHEA SpRAM RHEA reaches such performances thanks to the data retention mode, which supports a voltage as low as 0.77 V at 55 nm and 90 nm. This minimum voltage retention feature enables to divide leakage by 4 compared to alternative memory generators in stand-by mode.
If you want more information about the:
- SpRAM RHEA HD-RR TSMC 90 nm eFlash click here
- SpRAM RHEA HD-RR TSMC 55 nm eFlash click here
Or contact Dolphin Integration Library Marketing Manager at firstname.lastname@example.org
The SpRAM RHEA is part of a complete library portfolio covering
- at 55 nm eF: ultra high-density 6-track standard cells and their kit for islet construction, generators for Dual Port SRAM, via programmable ROM and regulators.
- at 90 nm eF: ultra high-density 6-track standard cells (1.2V +/-10%) and ultra low leakage standard cells (from 1.2V to 3.3V +/-10%) with their kit for islet construction, generators for Dual Port SRAM, one port and two port register file, via programmable ROM and linear regulators.
This panoply for eFlash process is completed by a unique cache controller, which allows to upgrade to 3 times faster and 3 times lesser power consumption compared to a stand alone eFlash memory.
About Dolphin Integration
Dolphin Integration contribute to "enabling mixed signal Systems-on-Chip". Their focus is to supply worldwide customers with fault-free, high-yield and reliable kits of CMOS Virtual Components of Silicon IP, based on innovative libraries of standard cells, flexible registers and low-power memories. They provide high-resolution converters for audio and measurement, regulators for efficient power supply networks, application optimized micro-controllers.
They put emphasis on resilience to noise and drastic reductions of power-consumption at system level, thanks to their own EDA solutions missing on the market for Application Hardware Modeling as well as early Power and Noise assessment. Such diverse experience in ASIC/SoC design and fabrication, plus privileged foundry portal even for small or medium volumes, makes them a genuine one-stop shop covering all customers’ needs for specific requests.