Ed Sperling, SemiEngineering
March 27th, 2014
From the leading edge of design to older process nodes, development costs are being contained much better than the initial reports would indicate. But not always for the obvious reasons.
From the most advanced process nodes to the trailing edge of design there is talk about the skyrocketing cost of developing increasingly complex SoCs. At 16/14nm it’s a combination of multi-patterning, multiple power domains and factoring in physical and proximity effects. At older nodes, it’s the shift to more sophisticated versions of the processes and new tools to work within those processes.
Despite an industry-wide sense of despair, though, progress is being made on all fronts—either with tools or methodologies or platform approaches that rely heavily on reuse. While projections show it will cost as much as $300 million to develop new SoCs at the leading edge (see chart below), the real numbers are generally much lower—generally between $20 million and $50 million, providing there is plenty of reusable IP. And at older nodes, improvements in processes can allow chipmakers to stay exactly where they are and still eke one or two generations of devices out of the same node. It’s not all good news — it’s still expensive, difficult and often frustrating — but neither is it all bad news.