New memory IP offers optimal protection against system downtime due to runtime memory failures
SANTA CLARA, Calif., April 21, 2014—Memoir Systems Inc., today introduced Renaissance Memory Uptime IP, a solution that protects against the growing threat of catastrophic memory failure due to multi-bit errors. The high performance SOCs at the heart of data center equipment are highly integrated and often have hundreds of megabits of embedded memory. In an industry that targets 99.999% system uptime, OEMs succeed or fail based on their ability to deliver highly reliable products, with no tolerance for system failure due to memory errors.
“The potential for cloud computing in mission critical environments is huge, but it comes with risks— system outages can lead to critical failure and can be costly,” said Awais Nemat, founder and CEO at PLUMgrid, a Cloud Networking start-up. “With many enterprise applications as well as mission critical medical, financial, and aeronautic applications moving to the cloud, the stakes have never been higher.” “Premier OEMs do not want to risk their reputations or incur the expensive consequences of system downtime due to catastrophic memory errors,” said Sundar Iyer, co-founder and CEO at Memoir. “They need a lightweight solution that protects against multi-bit failures during runtime.”
High end servers and networking equipment use ECC (Error Correction Code) memory protection primarily to correct soft or transient memory errors. However, traditional ECC corrects only single bit errors and is unable to correct multi-bit memory failures. This is a problem, particularly when a hard memory error occurs since a permanent single-bit error renders ECC ineffective against future errors at a given memory word.
Renaissance Memory Uptime uses Memoir’s Pattern Aware Memory Technology to provide a nonintrusive solution that is transparent to the designer. It exploits the principle that if single bit errors are guaranteed to be detected and corrected proactively within a tightly specified time window during runtime, then the probability of catastrophic memory errors can be proven to be dramatically reduced by orders of magnitude over the lifetime of the product.
Renaissance Memory Uptime provides an optimal solution for a wide variety of configurations, taking into account the memory type, width, depth, clock frequency, mean time to failure and many other design parameters. It is highly parameterized and field programmable. The solution exposes standard single or multi-port SRAM interfaces. It adds negligible gate count, and does not require any software intervention.
For OEMs that need to guarantee high system availability, Renaissance Memory Uptime offers an advanced solution that can dramatically reduce system downtime due to memory errors.
About Memoir Systems, Inc.
Memoir Systems, Inc. is a provider of breakthrough memory technology that is delivered as Semiconductor Intellectual Property (SIP). Memoir’s revolutionary approach to memory design shortens the time required to develop new memories, and can increase the performance of existing memory macros by up to 10X more Memory Operations Per Second (MOPS). The company’s Renaissance family of products provides drop-in replacements for existing embedded memories. These new memories offer increased performance or reduced area and power consumption without sacrificing performance. Memoir’s technology is optimized for a particular process, node, and foundry and integrates seamlessly into any existing SoC design flow. Since the introduction of the company in October of 2011, Memoir Systems has received several industry accolades and awards including: winning a DesignVision award at DesignCon in February 2012; named to EE Times “Silicon 60” list of emerging start-ups in April 2012 and named as A Red Herring Top 100 North America Tech Startup in May 2012. Memoir Systems is based in Santa Clara, California and has additional research and development facilities located in Hyderabad, India and Yerevan, Armenia. For more information, visit www.memoir-systems.com.