Altera Announces New FFT Intellectual Property Core for High-Performance Communications Applications
Altera's FFT Core Reaches New Performance Levels Utilizing the DSP Blocks in Stratix Devices
San Jose, Calif., June 18, 2002 -- Altera Corporation (NASDAQ: ALTR) today announced the immediate availability of its new fast Fourier transform (FFT) MegaCore® function, optimized for the Stratix™ device family. The new FFT version 1.3.0 intellectual property (IP) core is more than twice as fast as previous versions and consumes 50 percent fewer logic elements (LEs) when implemented in Stratix devices. These improvements were achieved by taking advantage of the DSP blocks in the Stratix architecture, including embedded multipliers, adders, subtractors, accumulators, and pipeline registers.
The Stratix DSP blocks are used to achieve high data throughput required for computationally demanding applications, providing a combined throughput of up to 56 giga multiply accumulate operations per second (GMACs)-- more than 10 times the rate available today from leading, standalone digital signal processors (DSPs).
"Altera is able to achieve a significant reduction in the number of consumed logic elements and realize major performance gains by utilizing the embedded DSP blocks in Stratix devices," said Justin Cowling, Altera's intellectual property marketing director. "In previous versions of the FFT core, multipliers were built from logic elements which contributed to the performance bottleneck."
The new FFT MegaCore function is suited for many digital signal processing applications such as local multi-point distribution system (LMDS), multi-point, multi-channel distribution system (MMDS), digital video broadcast - terrestrial (DVB-T), and medical and image processing. For example, an orthogonal frequency division multiplexing (OFDM)-based DVB-T application requires an 8K point FFT (with float width, data width, and twiddle width of five, 16, and 16, respectively) and transform times of 800 microseconds. Altera's new FFT core can be implemented as a multi-channel, 8K point FFT for as little as $8 in the Stratix EP1S10 device.
Altera customers also have access to Altera's new on-line resource that provides solutions for all their DSP design requirements. Now available at http://www.altera.com/solutions/dsp/dsp-index.html, the DSP Solution Center allows customers access to all DSP-related information in a central location.
About FFT Core
The Altera FFT MegaCore function is a parameterizeable IP core that implements a block floating point system for maximum accuracy. The core uses an in-place mixed radix four and two decimation in-frequency architecture, and implements any transform length that is a power of two. The core's control unit automatically implements partitioning between radix four and radix two passes.
The IP core comes with Altera's easy-to-use MegaWizard® Plug-In Manager tool, a parameterization tool that helps designers integrate megafunctions into their designs. Three reference designs, also included, show how to use the FFT core in different applications. More information about the FFT MegaCore logic function can be found at http://www.altera.com/products/ip/altera/m-ham-fft.html.
Pricing and Availability
The new FFT version 1.3.0 MegaCore function is available now for existing customers on valid maintenance. New customers can purchase and download the encrypted netlist, node-locked license for $7,995, which includes 12 months of upgrades.
About Stratix Devices
Altera's Stratix devices are based on a 1.5-V, 0.13-µm, all-layer copper SRAM process with densities ranging from 10,570 to 114,140 logic elements and up to 10 Mbits of RAM. Stratix devices offer up to 28 DSP blocks with up to 224 embedded multipliers, optimized for DSP applications that require high data processing. Stratix devices support various differential I/O electrical standards such as the LVDS, LVPECL, PCML, and HyperTransport™ standards, as well as high-speed interfaces including the UTOPIA IV, SPI-4 Phase 2, SFI-4, 10G Ethernet XSBI, RapidIO™, HyperTransport, and other interfaces.
Stratix device family support in the Quartus® II design software is available now. For more information about the Stratix device family, including a product backgrounder, answers to frequently asked questions and related white papers, visit: http://www.altera.com/corporate/news_room/nr-index.html.
About Altera
Altera Corporation (Nasdaq: ALTR) is the world's pioneer in system-on-a-programmable-chip (SOPC) solutions. Combining programmable logic technology with software tools, intellectual property, and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide. More information is available at http://www.altera.com.
|
Intel FPGA Hot IP
Related News
- Mentor Graphics and Altera announce Catapult C Synthesis Accelerated Libraries for High-Performance DSP Hardware in FPGA
- Altera to Feature High-Performance Memory Interface and PCI Express Solutions at Denali MemCon 2006
- NetEffect Uses Tensilica's Xtensa Processor Technology in High-Performance Ethernet Communications Products
- Altera Benchmarks Demonstrate Clear Performance Leadership in High-Performance FPGA Market
- Altera Ships Two New Intellectual Property Cores Targeting the Communications Market <!--<FONT SIZE=-1>(by Peter Clarke - EE-TIMES)</FONT>-->
Breaking News
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Leveraging Cryogenics and Photonics for Quantum Computing
- Kalray Joins Arm Total Design, Extending Collaboration with Arm on Accelerated AI Processing
- Credo at TSMC 2024 North America Technology Symposium
- Cadence Reports First Quarter 2024 Financial Results
Most Popular
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
- Silicon Creations Reaches Milestone of 10 Million Wafers in Production with TSMC
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Analog Bits to Demonstrate Numerous Test Chips Including Portfolio of Power Management and Embedded Clocking and High Accuracy Sensor IP in TSMC N3P Process at TSMC 2024 North America Technology Symposium
- Alphawave Semi: FY 2023 and 2024 YTD Trading Update and Notice of Results
E-mail This Article | Printer-Friendly Page |