Cadence Announces New Integrated Solution for Rapid Die-Package Interconnect Planning
Enables concurrent optimization of multi-fabric elements, leading to lower cost and higher performance
SAN JOSE, Calif., --21 May 2014 -- Cadence Design Systems, Inc., a leader in global electronic design innovation, today announced a new integrated solution to significantly cut down die-package interconnect planning time from weeks to days by reducing iterations between silicon and package design teams. The solution, built on Cadence® OrbitIO™ technology, also shortens the time to converge on the physical interface between the die and package up to 60 percent, all within the context of the full system.
Building on its leadership position for co-design in the implementation stage, Cadence OrbitIO technology is used earlier in the design cycle to provide rapid interconnect planning of high-performance interfaces across multiple fabrics. As part of an overall co-design solution, Cadence OrbitIO technology provides seamless integration with Cadence SiP Layout and the Cadence Encounter® digital implementation platform. This integrated solution allows design teams to clearly communicate design intent throughout the flow, resulting in better decision-making, fewer iterations and shorter cycle-times. It can enable fabless semiconductor or systems companies to evaluate package route feasibility, and allows them to communicate a route plan to their package design resources, whether it is to an internal group or to an outsourced assembly and test (OSAT) provider.
“The Cadence OrbitIO global view of system connectivity helps Faraday reduce the time required to converge on the optimal die bump to package ball pad assignment,” said Dr. Wang-Jin Chen, senior technologist of Faraday. “The combination of connectivity optimization and route feasibility functions helped us produce a route plan resulting in two fewer package layers with all DDR signals implemented on a single package layer.”
To learn more about OrbitIO technology, please visit: www.cadence.com/products/sigrity/orbitio/pages/default.aspx
About Cadence
Cadence (NASDAQ: CDNS) enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.
|
Cadence Hot IP
Related News
- Mixel Silicon-Proven MIPI IP Integrated Into ams OSRAM Mira Image Sensor Family Products Enabling Rapid Development of New Systems
- Cadence Announces Legato Memory Solution, Industry's First Integrated Memory Design and Verification Solution
- Cadence Expands Capabilities of Integrated Design and Analysis Flow for TSMC InFO Packaging Technology
- Cadence Enables Accelerated Implementation and Signoff of New ARM Cortex-M23 and Cortex-M33 Processors
- Cadence Delivers Integrated System Design Solution for TSMC InFO Packaging Technology
Breaking News
- Cadence Reports First Quarter 2024 Financial Results
- Rambus Advances AI 2.0 with GDDR7 Memory Controller IP
- Faraday Reports First Quarter 2024 Results
- RAAAM Memory Technologies Closes $4M Seed Round to Commercialize Super Cost Effective On-Chip Memory Solutions
- Alphawave Semi Audited Results for the Year Ended 31 December 2023
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Omni Design Technologies Joins Intel Foundry Accelerator IP Alliance
- Faraday Partners with Arm to Innovate AI-driven Vehicle ASICs
- Semiconductor Capacity Is Up, But Mind the Talent Gap
- Efabless Announces the Release of the OpenLane 2 Development Platform, Transforming Custom Silicon Design Flows
E-mail This Article | Printer-Friendly Page |