Rick Merritt, EETimes
6/30/2014 08:00 AM EDT
SAN JOSE, Calif. — The semiconductor road map is becoming as narrow and twisting as a mountain road, according to executives at two capital equipment companies. Chip vendors face higher costs and complexities due to tighter margins, new processes, and materials at 20 nm and beyond, they say.
In logic, foundries and their fabless customers have yet to settle on a new set of design rules. In memory, NAND flash has started a shift to 3D design other chips are likely to follow in some form, and DRAM faces a major materials shift, probably in 2015.
At 20 nanometers, the overlay budget of about 6 nm will shrink to about 4.5 nm while specifications for critical dimensions will narrow from 3 nm to 2 nm, says Brian Trafas, chief marketing officer at KLA-Tencor. He also predicts a 30% increase in process control spending between the 28 nm and 20 nm nodes to handle the requirements for multiple lithographic patterns needed to define some mask layers.
Chipmakers are using multi-patterning in four to ten mask layers starting at 20 nm and the follow-on node. In addition, these nodes are adding on a number of new deposition and etch steps, Trafas tells us.
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