IP And FinFETs At Advanced Nodes
Ed Sperling, Semiconductor Engineering
July 10th, 2014
Semiconductor Engineering sat down to discuss IP and finFETs at advanced nodes with Bernard Murphy, CTO of Atrenta; Warren Savage, president and CEO of IPextreme; Aveek Sarkar, vice president of engineering and product support at Ansys-Apache; Randy Smith, vice president of marketing at Sonics. What follows are excerpts of that conversation.
Related News
- IP And FinFETs At Advanced Nodes - Part 2
- Arm and Synopsys Strengthen Partnership to Accelerate Custom Silicon on Advanced Nodes
- Intel and Synopsys Expand Partnership to Enable Leading IP on Intel Advanced Process Nodes
- Cadence AI-Based Virtuoso Studio Certified for Samsung Foundry PDKs for Mature and Advanced Nodes
- Synopsys and Arm Strengthen Collaboration for Faster Bring-Up of Next-Generation Mobile SoC Designs on the Most Advanced Nodes
Breaking News
- Cadence Announces Most Comprehensive True Hybrid Cloud Solution to Provide Seamless Data Access and Management
- Dolphin Design expands GoAsic partnership to enhance the semiconductor Industry's Supply Chain
- Cadence Collaborates with MemVerge to Increase Resiliency and Cost-Optimization of Long-Running High-Memory EDA Jobs on AWS Spot Instances
- M31 Successfully Validates 5nm IP Solution to Empower Global AI Applications
- Cadence Unveils Palladium Z3 and Protium X3 Systems to Usher in a New Era of Accelerated Verification, Software Development and Digital Twins
Most Popular
- Rivos Raises More Than $250M Targeting Data Analytics and Generative AI Markets
- Semiconductor Capacity Is Up, But Mind the Talent Gap
- Zhuhai Chuangfeixin: OTP IP Based on 90nm CMOS Image Sensor Process Technology Successfully Mass Production
- CMC Microsystems and AIoT Canada Sign Memorandum of Understanding to support IoT and semiconductor ecosystem growth in Canada
- Microchip Technology Acquires Neuronix AI Labs
E-mail This Article | Printer-Friendly Page |