As SoC developers shift backward to established nodes, steps can be taken to improve the IPs functionality.
Ann Steffora Mutschler, Semiconductor Engineering
August 7th, 2014
Driven by the IoT and wearable market opportunity, SoC developers are shifting backward to established nodes, and what is learned at the leading-edge nodes is being leveraged in reverse as IP is ported backward to improve functionality.
IP certainly can be improved to work faster at older geometries, stressed Krishna Balachandran, product marketing director for low power at Cadence. “Threshold voltage manipulation like forward biasing has been selectively used to speed up critical portions of the IP at the expense of increased leakage that is restricted to those sections of the IP without significant overall impact. IP area also can be traded off for performance. Techniques range from layout design optimizations, like using larger channel transistors, to architectural duplication of functional units.”