32-Bit RISC-V Embedded Processor and Subsystem, Maps ARM M-0 to M-4. Optimal PPA,
Altera Releases Quartus II Software Arria 10 Edition v14.0
San Jose, Calif., August 18, 2014 – Altera Corporation (Nasdaq: ALTR) today released Quartus® II software Arria® 10 edition v14.0, the industry’s most advanced 20 nm FPGA and SoC design environment. Altera’s proven Quartus II software delivers the fastest compile times and enables the highest performance for 20 nm FPGA and SoC designs in the industry. Customers can further accelerate their Arria 10 FPGA and SoC design cycles by using the broad portfolio of 20 nm-optimized IP cores included in this latest software release.
Altera’s 20 nm design tools feature the most advanced algorithms and deliver the highest quality of results in the industry. The Quartus II software Arria 10 edition v14.0 provides on average 2X faster compile times compared to the nearest competitor’s 20 nm design software. This productivity advantage allows customers to shorten design iterations and rapidly close timing on their 20 nm design. The software also enables the highest performance 20 nm designs – providing customers more than a one-speed grade performance advantage over competitive FPGAs.
Included in the latest software release is a full complement of 20 nm-optimized IP cores to enable faster design cycles. The IP portfolio includes standard protocol and memory interfaces, DSP and SoC IP cores. Altera also optimized its popular best-in-class IP cores for Arria 10 FPGAs and SoCs, which include 100G Ethernet, 300G Interlaken, Interlaken Look-Aside and PCI Express Gen3 IP. When implemented in Altera’s Arria 10 FPGAs and SoCs, these best-in-class IP cores deliver the highest performance in the FPGA industry.
A full list of the features and capabilities offered in this software release can be found at http://www.altera.com/b/quartus-ii-arria-10-edition.html
Industry’s Highest Performance 20 nm FPGAs and SoCs
Arria 10 FPGAs and SoCs are the most advanced, highest-performance 20 nm FPGAs available today. The devices integrate several industry-leading features that make Arria 10 FPGAs and SoCs well suited to meet the requirements of high-end, high-performance systems.
- FPGA Industry’s Only 20 nm ARM-based SoCs – Arria 10 SoCs increase system integration by combining a 1.5 GHz dual-core ARM® Cortex™-A9 MPCore™ hard processor system (HPS) and embedded peripherals with FPGA logic, DSP blocks, high-speed interfaces and memory.
- Only FPGAs with Hardened IEEE 754 Floating Point DSP – Arria 10 FPGAs and SoCs deliver up to 1.5 TFLOPs of DSP performance to address an expanding range of computationally intensive applications in high-performance computing (HPC), radar, scientific and medical imaging.
- Highest Serial Bandwidth – Arria 10 FPGAs and SoCs deliver an industry-leading 3.6 Tbps of serial bandwidth with 96 transceiver lanes, the most transceiver lanes and bandwidth in its class.
Pricing and Availability
The Quartus II software Arria 10 edition v14.0 is available now for download at www.altera.com/quartus-arria10. The software is available as a subscription edition and includes a free 30-day trial. The annual software subscription is $2,995 for a node-locked PC license. Engineering samples of Arria 10 FPGAs are shipping today. For additional information about Arria 10 devices, contact your local Altera sales representative or visit www.altera.com/arria10.
|
Intel FPGA Hot IP
Related News
- Altera Enables Immediate 20 nm Design Starts with Quartus II Software Arria 10 Edition
- Altera's Quartus II Software Version 11.1 Delivers Arria V and Cyclone V FPGA Support and Productivity Improvements
- Altera's Quartus II Software Version 10.0 Delivers Unprecedented Performance and Productivity for High-End FPGAs
- Altera Announces New Spectra-Q Engine for Industry-leading Quartus II Software to Accelerate FPGA and SoC Design
- Altera Quartus II Software v14.1 Enables TFLOPS Performance in Industry's First FPGA with Hardened Floating Point DSP Blocks
Breaking News
Most Popular
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
- Silicon Creations Reaches Milestone of 10 Million Wafers in Production with TSMC
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Analog Bits to Demonstrate Numerous Test Chips Including Portfolio of Power Management and Embedded Clocking and High Accuracy Sensor IP in TSMC N3P Process at TSMC 2024 North America Technology Symposium
- Alphawave Semi: FY 2023 and 2024 YTD Trading Update and Notice of Results
E-mail This Article | Printer-Friendly Page |