32-Bit RISC-V Embedded Processor and Subsystem, Maps ARM M-0 to M-4. Optimal PPA,
Cadence's Rowen Forecasts Processor Design Split
Peter Clarke (Electronics360)
22 September 2014
Chris Rowen, CTO of the IP Group at Cadence Design Systems Inc. (San Jose, Calif.), has developed a vision of how system-on-chip architecture is evolving in the era of the Internet of Things and has concluded that processor architectures will become more diverse and their design style will bifurcate into least two major categories. Rowen added that this vision is driving future product development at Cadence.
One example is that neural network processor architecture is being worked on at Cadence as part of research into how much diversity is required to serve the market, Rowan said. However, he added that there at present no plans or timetable for the introduction of a configurable neural network processor IP block.
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