National's new info-appliance MPU packs enhanced x86 core, power management

National's new info-appliance MPU packs enhanced x86 core, power management
By Semiconductor Business News
October 15, 2001 (6:28 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011015S0073

SAN JOSE -- Pushing ahead with its information appliances chip strategy, National Semiconductor Corp. this week will officially launch its new Geode GX2 series of integrated processors, based on a re-engineered x86-based core, 0.15-micron process technology, and a new modular architecture with built-in power management circuits.

The Geode GX2 integrated processor and companion chip (for I/O bus and peripheral control) will be priced together at less than $50 each in high-volume quantities. Production is expected to begin in the first half of 2002, according to National, which will introduce the GX2 at this week's Microprocessor Forum in San Jose.

National's second-generation Geode processor contains the new GeodeLink Advanced Hardware Power Management unit, which can shut down portions of the IC "depending upon the need for activity at any given time to save power," said Yves Gourvennec, marketing manager for the series.

To soup up the x86 p rocessor core, National has improved the floating-point unit, enhanced pipeline instructions and optimized the integer unit of the central processor, he said. The new floating-point unit has added 3DNow! multimedia support.

"In the information appliance processor, there is a need to have enough horse power to handle all the applications that will be thrown at it--plug-ins, HTML, Java, JavaScript , Windows Media Player, and more," Gourvennec said. He said many of the older PC processor chips aimed at information appliances are not powerful enough, and other RISC-based offerings do not have enough functions on chip.

In addition to the enhanced x86 CPU, the GX2 processor integrates a new high-speed GeodeLink on-chip switch fabric with up to 6-gigabyte-per-second bandwidth between functions on the device. National said the processor also contains integrated graphic controller and digital-to-analog converters (DACs) as well as level 1 cache of 32-kilobytes (16 Kbytes for instructions and 16 Kbytes for dat a). The processor will have a typical power dissipation of 820 milliwatts with its core voltage at 1 V and I/Os at 3.3 volts, said the Santa Clara, Calif.-based chip company.

The processor will be housed in a 368-ball EBGA package and the companion device in a 208-ball PBGA. Samples of the integrated processor will be made available in the fourth quarter this year, and the first system applications are expected to be announced in Q1.