H.264 High Profiles Encoder - High 10, High 4:2:2 and High 4:4:4 (12 bit 4:2:2 or 4:2:0) Profiles
HiSilicon Chooses Synopsys' PrimeTime ADV for Faster Timing Closure
Achieves Single-pass Timing and Power ECO Closure on Multiple Tapeouts Including FinFET
MOUNTAIN VIEW, Calif., Oct. 8, 2014 -- Synopsys, Inc. (Nasdaq: SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced that HiSilicon Technologies, a leading end-to-end chipset solution provider for telecom network, wireless terminal and digital media, has chosen Synopsys' PrimeTime® ADV product for timing closure. The latest technology innovations in PrimeTime ADV, including signoff-driven, physically-aware engineering change order (ECO) and power recovery, were essential to accelerating design closure on key HiSilicon projects.
"At HiSilicon, time-to-market is a critical factor of our success in the competitive communications market," said Bruce Bin, sr. director, HiSilicon Technologies Co., Ltd. "Deploying a design flow that delivers fast, high-quality results can accelerate our design cycle by valuable weeks. As a result, we have chosen PrimeTime ADV for our design closure flow for all projects at various technology nodes. On a recent 16-nm FinFET tapeout, PrimeTime ADV provided fast, accurate and predictable design closure that helped us reach aggressive performance and power targets on time."
HiSilicon has deployed new PrimeTime technologies to ensure signoff-accurate and rapid design closure with Synopsys' Galaxy™ Design Platform, including:
- Advanced waveform propagation for signoff-accurate results on FinFET designs, including impact of increased Miller effect and resistance
- Placement density-aware ECO to achieve a 99.7 percent single-pass fix rate and excellent convergence with IC Compiler™ minimal physical impact (MPI) technology, resulting in 0.1 micrometer average cell movement
- Route-based ECO insertion to provide best QoR and minimize route change during IC Compiler ECO implementation
- Leakage recovery to reduce leakage power up to 10 percent in addition to IC Compiler final-stage leakage recovery with no signoff timing impact
"HiSilicon is one of the leading chipset solution providers in the competitive wireless and networking markets, where timing closure is a key focus," said Antun Domic, senior vice president and general manager, Synopsys Design Group. "Our partnership with HiSilicon has benefitted both companies by creating unique technologies in PrimeTime ADV, and we are pleased that they have chosen it for their design closure flow."
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) accelerates innovation in the global electronics market. As a leader in electronic design automation (EDA) and semiconductor IP, its software, IP and services help engineers address their design, verification, system and manufacturing challenges. Since 1986, engineers around the world have been using Synopsys technology to design and create billions of chips and systems. Learn more at www.synopsys.com.
|
Synopsys, Inc. Hot Verification IP
Related News
- Synopsys' PrimeTime ADV Achieves Rapid Adoption for Fastest Timing Closure
- Synopsys' PrimeTime Speeds Timing and Power Closure for Complex SoC and IoT Designs
- Synopsys PrimeTime Advanced On-chip Variation Analysis Enables Renesas to Accelerate Timing Closure at 65-nm and Below
- Actel's Axcelerator FPGAs Gain Greater Performance and Faster Timing Closure with Latest Libero Design Environment
- Synopsys Delivers 100X Faster Formal Verification Closure for AI, Graphics, and Processor Designs
Breaking News
- PUFsecurity Unveils Next-Gen Crypto Coprocessor PUFcc7 Featuring High-speed Performance and TLS 1.3 Support
- SEMIFIVE Starts Mass Production of its 14nm AI Inference SoC Platform based Product
- VeriSilicon's complete Bluetooth Low Energy IP solution is fully compliant with LE Audio specification
- TASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP
- Efabless Launches an "AI Wake Up Call" Open-Source Silicon Design Challenge
Most Popular
- Intel and Arm Team Up to Power Startups
- Chiplet Interconnect Pioneer Eliyan Closes $60 Million Series B Funding Round, Co-led by Samsung Catalyst Fund and Tiger Global Management to Address Most Pressing Challenge in Development of Generative AI Chips
- PUFsecurity Unveils Next-Gen Crypto Coprocessor PUFcc7 Featuring High-speed Performance and TLS 1.3 Support
- Renesas Introduces Industry's First General-Purpose 32-bit RISC-V MCUs with Internally Developed CPU Core
- SmartSoC Solutions Joins TSMC Design Center Alliance to Boost Semiconductor Innovation in India
E-mail This Article | Printer-Friendly Page |