HDL Design House New Verification Seminar in Switzerland: Maximizing Verification Efficiency

Belgrade, Serbia – November 13^th, 2014 - HDL Design House is organizing a free full day verification seminar in Switzerland, taking place at Boldern conference center on November 25^th, 2014. The seminar will include presentations from HDL Design House, Cadence, Mentor Graphics and Sensirion verification experts, addressing topics related to maximization of verification efficiency.

When/Where:
Tuesday, November 25^th, 2014
9.00 am - 4.00 pm, lunch included
Boldern conference center
Tagungszentrum
Boldernstrasse 83
CH-8708 Männedorf
http://www.boldern.ch

To register for the seminar please visit:

http://www.hdl-dh.com/seminar5.html

Participation is free of charge. Lunch and refreshments will be served.

The seminar is relevant for design & verification managers and engineers and semiconductor professionals.

Agenda and Speakers' Topics:

9.00 - 9.30 Coffee & Registration

9.30 - 09.45 Introduction
Predrag Markovic, HDL DH CEO and Frank Werner, HDL DH Account Manager

9.45 - 10.30 Integration and Verification-Focused for Reduced Risk
Manfred Lehmann, Senior Account Executive at Cadence Design Systems
Integration of IP has traditionally been a challenge for SoC designers. By building our IP from the ground up, and by focusing on integration, we help you significantly reduce both integration effort and risk. In addition, our ability to deliver fully integrated controller, PHY, and firmware solutions at both the interface and subsystem level further reduces your integration effort.
One of the most time-consuming aspects of SoC verification is creating a testbench that models the SoC's interfaces. Since a typical SoC may contain several interfaces such as DDR, USB, or I2C, modeling all those interfaces is extremely time-consuming. VIP provides a huge benefit by modeling all those interfaces as components that can be plugged into an SoC testbench and simulated along with the chip.

10.30 - 12.30 Verification Process Enhancement
Olivera Stojanovic, Senior Staff Verification Engineer, HDL DH
Marko Olujic, Senior Verification Engineer, HDL DH
This presentation shows how to maximize verification effectiveness in conjunction with the UVM. Besides standard UVM approach of reusing UVCs through different projects, the presentation introduces different flavors of reuse. The presentation demonstrates ways how to speed up verification environment implementation, debug process and decrease simulation time.

12.30 - 13.30 Lunch

13.30 – 14.30 We all like changes! Let's get the most out of them!
Josef Derner, Global Business Development Manager at Mentor Graphics
Over the last 10 years Functional Verification has changed significantly with the introduction of SystemVerilog, the different open source verification methodologies (AVM / OVM / UVM (1.1/1.2), IEEE 1801, and UCIS. The adoption of the current standards and the changes in the verification industry can be seen in the different Wilson Research studies including the newest 2014 version.
Mentor Graphics is a key driver and supporter all of these important standards. Time to coverage, functional verification efficiency and reduced debugging effort are the key challenges of the functional verification community. Mentor Graphics addresses with the Enterprise Verification platform these different challenges through putting the verification engines for simulation, emulation, formal verification to the task.

14.30 – 15.30 Coverage Reuse for SOC Verification
Inan Erdem, ASIC Design Engineer at Sensirion
Defining coverage model and then reaching to a high percentage coverage at IP-level is relatively straightforward, but for SOC-level verification one has to create more scenario driven coverage model. Scenario driven coverage models are generally valid for only a specific scenario and are not suitable for re-use. Therefore one has to somehow layer them just like we layer UVM sequences.
The approach we took at Sensirion addressed this issue by defining different types of low-level coverage models and then re-use them at higher levels in a scenario context. Coverage sampling is also separated into layers,where low-level coverages are sampled mainly in a concurrent process, while higher level coverages are sampled via a remote-sampling mechanism where sampling event is created in a context aware fashion.

15.30 - 16.00 Coffee & Networking

About HDL Design House

HDL Design House delivers leading-edge digital and analog design and verification services and products in numerous areas of SoC and complex FPGA designs. The company also develops IP cores and offers back-end services. The company has extensive experience with the ARM CPU architecture, ARM CPU processor interfaces and development or integration of SoC based on ARM CPU. Founded in 2001 and currently employing 100 engineers working in two design centers in Serbia, HDL Design House mission is to deliver high quality products and services, with flexible licensing models, competitive pricing and responsible technical support. The company was awarded ISO 9001:2008 and ISO 27001:2005 certifications in December 2006/2009/2012. For more information, please visit www.hdl-dh.com