Improv's Jazz DSP Tops EEMBC's Telecom Benchmark

Configurable DSP Core Recognized as Most Efficient Processor

Beverly, Mass -- August 5, 2002 -- Improv Systems™, a pioneer in application-optimized DSPs, today announced it completed the Embedded Microprocessor Benchmark Consortium (EEMBC) Telecom benchmark certification process for its Jazz™ 2020 Processor and achieved the highest speed rating per cycle of any processor ever certified. Measured by performance per clock cycle, the Jazz processor is 40 percent more efficient than the TI C62 and nearly 20 percent more efficient than the Motorola MPC 7455 PowerPC and Carmel from Infineon. Also, the 'Out-of-the-Box' scores for the Jazz DSP™ were three times more efficient than micro-controllers such as ARM10, ARC, and Tensilica cores.
 

 

"The EEMBC Telecom benchmark study confirms what we and our customers have known all along. Our architecture is ideally suited to meet the requirements of today's compute-intensive embedded consumer and telecom applications," said Oz Levia, Chief Technical Officer, Improv Systems. "We made the investment early on to create a complete development environment that includes tools and methodology, which is why we were able to perform so well in this benchmark and why we are able to continually attract new licensees to the architecture."

 

The EEMBC Telecom benchmark suite is recognized by the industry as a significant barometer of real world performance because it is based on real application code and is developed with the input of its membership, which ensures the tests are fair and relevant. EEMBC's members include more than 55 of the world's leading semiconductor, intellectual property and compiler companies. In addition, the independent EEMBC Certification Labs (ECL) monitors the benchmark process to certify that the consortium rules are strictly followed and that the results are repeatable and verifiable.

 

"The EEMBC Certification Laboratories has certified Improv's Jazz 2020 using their cycle-accurate simulator," said ECL Chairman and CTO Alan R. Weiss. "Their 'Out-of-the-Box' (standard C) scores were extremely impressive: per megahertz (MHz), the Jazz processor beat everyone else who has been benchmarked and certified (simulator or hardware) to date for the EEMBC 'Out-of-the-Box' Telecom suite. Because their software tools are easy to use and performed flawlessly, the certification was very straightforward. If anyone doubts configurable, scalable processors, they need only go to the EEMBC Web site for hard data that proves their worth and shows how the gap is closing between hard-wired and programmable processors."

 

The EEMBC Telecom benchmark measures the speed at which processors handle a variety of tasks. To test different aspects of the processor and the tool chain, EEMBC allows two sets of data to be presented for each benchmark: 'Out-of-the-Box', meaning tests are run in a high-level language with no code modifications; and 'Full Fury', where any optimization that can be done by a developer/customer is allowed and an assembler can be used to speed things up, as long as the fundamental benchmark is still performed. Typically, optimized testing produces results 20 to 100 times faster than 'Out-of-the-Box' testing.

 

In this benchmark, Improv submitted a standard, two-slot configuration of its Jazz architecture, featuring two processing slots, each of which may execute a SHIFT, ALU, or MAC operation during each cycle. Improv plans to certify its processor under the EEMBC optimized procedure in the near future and initial data shows that the results will again surpass all other industry processors in throughput per cycle.

 

"By providing hard, unbiased data on a wide cross-section of processors and how they perform in embedded applications, EEMBC plays an important role in the electronics industry. I'm proud of the work we've done to help end-users in the difficult process of selecting the best fit for their applications," said Markus Levy, EEMBC President. "Improv's strong performance in the Telecom benchmark suite is a good example of the value of these types of evaluations. By achieving the level of efficiency it did, Improv changes the parameters of DSP design and compiler capabilities."

 

All applications for the Jazz processors are written in a high-level language. Targeting to specific configurations, including multi-processor systems, is handled by the Jazz PSA™ Compiler, although a single processor was used in this benchmark case. This compiler has the unique ability to allocate tasks and memory for maximum parallelism. All inter-processor communication is scheduled without the need for assembly code. Improv ran the EEMBC Telecom benchmark completely in a high-level language with no added or substituted assembly code or intrinsics.

 

Complete benchmark data on all EEMBC certified processors may be obtained by visiting the EEMBC Web site, www.eembc.org. Specific information about the Improv products can be obtained from the company's Web site, www.improvsys.com/eembcbenchmark.cfm . Benchmarking fairness is provided through the ECL ( http://www.ebenchmarks.com ).

 

About EEMB

EMBC, the Embedded Microprocessor Benchmark Consortium, develops and certifies real-world benchmarks and benchmark scores to help designers select the right embedded processors for their systems. Every processor submitted for EEMBC® benchmarking is tested for parameters representing different workloads and capabilities in communications, networking, consumer, office automation, automotive/industrial, embedded Java, and microcontroller-related applications. With members including leading semiconductor, intellectual property, and compiler companies, EEMBC establishes benchmark standards and provides certified benchmarking results through the EEMBC Certification Labs (ECL) in Texas and California.
 
About Improv Systems, Inc.

Improv Systems, Inc. develops and licenses the Jazz PSATM platforms featuring the Jazz DSP and application solution kits for Voice-over-IP, Networking and Emerging Media. Improv's Jazz DSP is a configurable DSP that allows designers to create optimized DSP cores targeted to consumer electronics and telecommunications markets. Through the company's Ensemble™ Partners program, formed to help accelerate the use and integration of designer-defined DSPs in System-on-Chip (SoC) solutions, Improv customers have access to complementary products and services from companies such as ARM (ARMHY), MIPS Technologies (MIPS, MIPSB), Synopsys (SNPS), Cadence Design Systems (CDN); and Wind River Systems (WIND) among others. Improv Systems has development centers in Beverly, MA, San Jose, CA, and Rochester, NY, and direct sales offices in the United Kingdom and Japan.

 

Improv, Ensemble, designer-defined DSPs, Jazz DSP, Jazz PSA , Acappella and Crescendo are registered trademarks or trademarks of Improv Systems, Inc. in the United States and/or other countries. Product and company names mentioned herein are trademarks and/or registered trademarks of their respective companies

 
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