Altera kicks off mask-programmable PLD program

Altera kicks off mask-programmable PLD program
By Anthony Cataldo, EE Times
October 11, 2001 (1:31 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011010S0061

SAN JOSE, Calif. — Programmable-logic vendor Altera Corp. this week unveiled its plan to give high-volume customers a migration path to lower-cost mask-programmable devices. By doing so, the company has acknowledged that when it comes to converting programmable logic devices (PLDs) to hardwired devices, it's better to join the cause than fight it.

But unlike gate array and FPGA-to-ASIC vendors, Altera's HardCopy program is being billed as a way to make a smoother transition to mask-programmable devices by preserving all but the routing structure of the original PLD prototype.

Using this approach, Altera claims it can slash the size of the device by 70 percent while keeping it functionally identical to the original PLD design. The San Jose company is now taking orders for mask-programmable devices based on its Apex architecture and will accept orders for its Apex 2 and Excalibur families next year.

To reduce device size, the company str ips out hardware that enables bit-stream programming of interconnect, logic and memory. The device is instead configured using six metal mask layers, similar to a gate array.

But Altera stressed that HardCopy is not a gate-array conversion in the strict sense, because it is built on the same logic elements, memory, I/Os, phase-locked loops, intellectual property, packaging and process technology as the original.

"You can still see all the logic elements," said Tim Colleran, Altera's vice president of product marketing. "If you go to a conversion process, you're using gates. It is fundamentally different."

A combination of hardware and software techniques is used to meet timing specifications, which have proved a tough issue when moving from a programmable-logic fabric to hardwired ASICs. HardCopy devices include built-in self-test, scan chains, automated test-program generators and preplaced clock trees.

Moreover, Altera has developed a way to convert an SRAM programming file generated fro m the company's Quartus 2 development software to various netlist formats. These netlists are then worked into an ASIC flow that includes tools for static timing analysis, formal verification, test insertion and design-rule checking.

All told, the company said it can sign off a prototype for mass production in eight weeks.

Altera said two customers have signed up for the program. One, Extreme Networks, is using six Apex-based mask-programmed ASICs for a new Layer 4-through-7 switch. The company was able to first send out sample switches to alpha and beta customers using conventional PLDs, then ship systems based on mask-programmed devices 16 weeks after starting the migration process, said Herb Schneider, vice president of engineering for Extreme.

Hardwired logic gave the design a performance that couldn't be matched by a network processor, he said. "We looked at four network processors but they did not give us enough cycles per packet to do what we wanted," Schneider said.

By coming out wi th a mask-programmable alternative, Altera is hoping to reach more top-tier customers that want to drive costs out of their systems. Programmable logic is often the first on the list of areas to reduce cost, particularly high-end devices that run in the thousands of dollars. Some of Altera's Apex 20K parts that are now shipping, for example, can cost more than $4,000.

"Last year it was all about time-to-market," said John Daane, Altera's president and chief executive officer. "This year it's about time-to-market and cost reduction."

To be sure, customers that choose to go with Altera's mask-programmable parts will have to pay nonrecurring-engineering charges of anywhere from $100,000 to $200,000. The company also requires minimum-volume purchases starting in the "few thousands," Colleran said.

But Altera claims its NRE costs and minimum-volume orders are only a fraction of what standard-cell ASIC companies require. Only in applications that call for very high volumes, such as game consoles or cel lular phones, will it be difficult for HardCopy to beat standard-cell ASICs, Daane said.

"For extreme volumes, standard-cell is still the best solution," Daane said. "But for the gate array vendors and conversion vendors — it's over for them."