USB V3.1 Power Delivery Type-C Port Evaluation board for OTI9108 IP
Cadence Announces Collaboration with TSMC on IoT IP Subsystem
SAN JOSE, Calif., June 8, 2015— Cadence Design Systems, Inc. (NASDAQ: CDNS), today announced that it is collaborating with TSMC on the development of an Internet of Things (IoT) intellectual property (IP) subsystem demonstration platform for TSMC’s ultra-low power (ULP) process. Targeting wearable, home automation, always-on and industrial control applications, this IP subsystem, with the support of the Cadence® suite of digital and custom/analog tools, provides the opportunity to simplify IoT designs and accelerate the time to market for mutual customers.
Initially targeting the TSMC 55ULP process, the flexible Cadence IoT IP subsystem will include the Cadence Tensilica Fusion digital signal processor (DSP), analog interfaces, peripheral and sensor interfaces. The flexibility of the subsystem will also allow users the option to select an applications processor if needed for their design. This Cadence IoT IP subsystem can also be implemented in 40ULP and 28ULP as additional performance is needed for more compute intensive applications in the future. Many of the 200+ Cadence Tensilica processor licensees are already designing and producing SoCs and end products in IoT applications; such products include WiFi/IoT connectivity chips, motion plus voice sensor fusion devices, and wearables including smart watches. Some of these next generation devices will be implemented in TSMC 55ULP over the next twelve months as the IP enablement gets more mature.
Cadence’s Fusion DSP includes configurable options for security algorithm acceleration, wireless communications protocol processing, and ultra-low power voice trigger. The Fusion DSP includes configurable I/O interfaces that allow direct connection to sensor interfaces and I2C and I2S serial interface controllers. The Fusion DSP including TSMC reference flow scripts and companion software development tools is available now.
“With our extensive library of processor, analog, memory, and interface IP, Cadence is in a unique position to team with TSMC to create IP subsystems that give designers the ability to rapidly develop creative IoT and consumer application SoCs,” said Martin Lund, senior vice president and general manager of the IP Group at Cadence.
“By collaborating with Cadence on the development of this IoT IP subsystem, we are enabling our mutual customers to quickly take advantage of the ultra-low power benefits of the 55 ULP process for their innovative designs,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division.
Cadence processor IP and interface IP for TSMC’s portfolio of process technologies is available now. For more information on Cadence IP, visit http://www.ip.cadence.com.
|
Cadence Hot IP
Related News
- ARM and Cadence Expand Collaboration for IoT and Wearable Device Applications Targeting TSMC's Ultra-Low Power Technology Platform
- Cadence Extends Collaboration with TSMC and Microsoft to Advance Giga-Scale Physical Verification in the Cloud
- Cadence Expands Collaboration with TSMC and Microsoft to Accelerate Timing Signoff for Giga-Scale Designs on the Cloud
- Cadence LPDDR4/4X Memory IP Subsystem Achieves ISO 26262 ASIL C Certification from SGS-TUV Saar Using TSMC 16FFC Process Technology
- Sequans Extends Collaboration with TSMC to Develop World's first LTE-M chip for IoT
Breaking News
- Cadence Announces Most Comprehensive True Hybrid Cloud Solution to Provide Seamless Data Access and Management
- Dolphin Design expands GoAsic partnership to enhance the semiconductor Industry's Supply Chain
- Cadence Collaborates with MemVerge to Increase Resiliency and Cost-Optimization of Long-Running High-Memory EDA Jobs on AWS Spot Instances
- M31 Successfully Validates 5nm IP Solution to Empower Global AI Applications
- Cadence Unveils Palladium Z3 and Protium X3 Systems to Usher in a New Era of Accelerated Verification, Software Development and Digital Twins
Most Popular
- Rivos Raises More Than $250M Targeting Data Analytics and Generative AI Markets
- Semiconductor Capacity Is Up, But Mind the Talent Gap
- Zhuhai Chuangfeixin: OTP IP Based on 90nm CMOS Image Sensor Process Technology Successfully Mass Production
- CMC Microsystems and AIoT Canada Sign Memorandum of Understanding to support IoT and semiconductor ecosystem growth in Canada
- Microchip Technology Acquires Neuronix AI Labs
E-mail This Article | Printer-Friendly Page |