RISC vs CISC: What's the Difference?
Analysis of ARM, X86, MIPS designs shows no difference
Bernard Cole, Editor of the EE Times' Microcontroller and Printed Circuit Board Designlines
EETimes (6/30/2015 06:07 PM EDT)
A new study comparing the Intel X86, the ARM and MIPS CPUs finds that microarchitecture is more important than instruction set architecture, RISC or CISC.
If you are one of the few hardware or software developers out there who still think that instruction set architectures, reduced (RISC) or complex (CISC), have any significant effect on the power, energy or performance of your processor-based designs, forget it.
Ain't true. What is more important is the processor microarchitecture — the way those instructions are hardwired into the processor and what has been added to help them achieve a specific goal.
This is the over-arching conclusion of a study recently published in the ACM Transactions on Computer Systems. In the paper, "ISA Wars: Understanding the Relevance of ISA being CISC or RISC," authors Emily Blem, Jakrishnan Menon, Thiruvengadam Vijayaraghavan, and Karthhikeyan Sankaralingam, report the results of a study over the last four years or so by the University of Wisconsin (Maidison) Vertical Research Group(VRG).
E-mail This Article | Printer-Friendly Page |
Related News
- ARM versus Intel: a successful stratagem for RISC or grist for CISC's tricks?
- What does Renesas' acquisition of PCB toolmaker Altium mean?
- What's driving the acquisitions in the analog design realm?
- Do more with less energy! What's behind Dolphin Design's Energy Efficient Platforms?
- After Moore's Law - What?
Breaking News
- China's Intel, AMD Ban Helps Local Rivals, Analysts Say
- PUFsecurity Unveils Next-Gen Crypto Coprocessor PUFcc7 Featuring High-speed Performance and TLS 1.3 Support
- SEMIFIVE Starts Mass Production of its 14nm AI Inference SoC Platform based Product
- VeriSilicon's complete Bluetooth Low Energy IP solution is fully compliant with LE Audio specification
- TASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP
Most Popular
- Intel and Arm Team Up to Power Startups
- Chiplet Interconnect Pioneer Eliyan Closes $60 Million Series B Funding Round, Co-led by Samsung Catalyst Fund and Tiger Global Management to Address Most Pressing Challenge in Development of Generative AI Chips
- PUFsecurity Unveils Next-Gen Crypto Coprocessor PUFcc7 Featuring High-speed Performance and TLS 1.3 Support
- Renesas Introduces Industry's First General-Purpose 32-bit RISC-V MCUs with Internally Developed CPU Core
- SmartSoC Solutions Joins TSMC Design Center Alliance to Boost Semiconductor Innovation in India