Accellera Systems Initiative Delivers UVM 1.2 to IEEE for Standardization

IEEE P1800.2™ working group issues Call for Participation

Elk Grove, Calif., July 30, 2015 – IEEE Standards Association (IEEE-SA) and Accellera Systems Initiative (Accellera), the electronics industry organization focused on electronic design automation (EDA) and intellectual property (IP) standards, announced today that the Accellera Universal Verification Methodology (UVM) 1.2 will be submitted as a contribution to the IEEE P1800.2™ working group for further standardization and maintenance once the working group has been established at its first meeting on August 6, 2015. A Call for Participation has been distributed for the first meeting.

UVM 1.2 builds on the IEEE 1800™ SystemVerilog standard by specifying an application programming interface that defines a base class library using the SystemVerilog language constructs. Design and verification teams can then use the library to develop modular, scalable and reusable components for functional verification environments. SystemVerilog has been in use by the industry for more than a decade, and UVM has become an important companion to foster greater global adoption of it. Under the IEEE Get Program, supported by Accellera, the IEEE 1800-2012 SystemVerilog standard specification has had more than 21,000 fee-free downloads. UVM also has a community of 6,700 verification professionals on LinkedIn.

"This is a significant milestone for Accellera," stated Shishpal Rawat, Accellera Systems Initiative chair. "We have seen rapid adoption of UVM across the global electronic design verification community. As Accellera transfers the ongoing standardization and maintenance to the IEEE, it will continue to maintain the open-source BCL and keep it current with any changes proposed during the IEEE standardization process."

“The collaboration between the IEEE Standards Association and Accellera continues to enhance the standards available to and used by electronic design teams around the world,” said Dr. Konstantinos Karachalios, managing director, IEEE-SA. “After a decade of outstanding IEEE 1800 adoption, we are pleased to launch another corporate-based standards project that will further enhance this foundational standard. We are looking forward to the first meeting of the IEEE P1800.2 working group and encourage all organizations interested in advancing innovation in electronic design—regardless of their size or geographic market globally—to join the group.”

About UVM

UVM addresses verification complexity and interoperability. It is a set of Application Programming Interfaces (APIs) that define a Base Class Library (BCL) definition used to develop modular, scalable and reusable components for functional verification environments. The UVM standard will improve interoperability and make it easier to reuse verification components, helping to lower verification costs and improve design quality.

About IEEE-SA

The IEEE Standards Association, a globally recognized standards-setting body within IEEE, develops consensus standards through an open process that engages industry and brings together a broad stakeholder community. IEEE standards set specifications and best practices based on current scientific and technological knowledge. The IEEE-SA has a portfolio of over 1,100 active standards and more than 500 standards under development. For more information visit http://standards.ieee.org.

About Accellera Systems Initiative
Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote and advance system-level design, modeling and verification standards for use by the worldwide electronics industry. The organization accelerates standards development and, as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit www.accellera.org. Find out more about membership.