Mn_nH release AXI chip-to-chip interface IP and HEVC encoding expand up to 8K 30fps

December 28, 2015 -- Mn_nH release X2X AXI interconnection IP for chip to chip communication. X2X AXI chip to chip interface IP enable equivalent AXI functionality and performance but less I/O usage with raising the rate of utilisation of AXI signal. And X2X IP provide system to system, cpu to cpu and bus to bus freely accessible functions between chip and another chip.

These days, Moore’s law is slowing down and cost per transistor is rising despite of more micro fab process.
If IC’s mass production quantity will be not enough for optimal cost point at specific micro fab process, IC maker can’t stake their all at once design because large scaled IC require high design cost, large die size and low reusability at the latest micro process. So now chip’s expandability and reusability is becoming more and more important.

Mn_nH’s X2X AXI chip to chip interface IP make muliple chips operate like as one chip with AXI interfacing between chip and another chip. X2X’s system to system freely accessibility maximise chip’s expandability and reusability and apply to ASIC prototyping with multiple FPGA, AP system connected with heterogeneous multiple chips or parallel processing with same multiple chips.

X2X AXI chip to chip interface IP can be used for a variety of applications. Suppose Mn_nH’s HEVC encoder IP for 4K 30fps expand performance up 4K 60fps or 8K 30fps with X2X collaboration. This expandability help IC maker’s product planning and targeting have more flexible. Usually high performance application is unmarketable but leading market and middle-end performance application is high demand but a short life. Now, Mn_nH’s X2X and HEVC encoder collaboration suggest optimal HEVC encoder architecture to target both application at the present moment.

Mn_nH’s X2X AXI chip to chip interface IP and HEVC encoder IP are licensed 2 fabless customer and expected to start mass production at 2Q of 2016.