Silicon Logic Engineering Launches Semiconductor Intellectual Property Simulation Environment to Assist High End Systems Developers

Interconnect for 10 Gigabit Applications (SPI-4 Phase 2), First in Series of Crucial Models Available Online; Interoperability Verified by Ample Communications Inc.

EAU CLAIRE, Wis., September 16, 2002 - Silicon Logic Engineering (SLE), a provider of high-end digital application specific integrated circuit (ASIC) and system-on-chip (SOC) design services, today announced the availability of SLE's model simulation environment, which allows high end systems engineers to "test drive" SLE's semiconductor intellectual property (SIP) cores to determine if they meet system specifications and interoperability requirements. SLE's model simulation environment is accessible immediately at www.siliconlogic.com through a unique, easy-to-use download procedure.

Unlike other test methods for commercially available SIP that require an upfront financial outlay, SLE's model simulation environment offers a risk-and cost-free alternative for verifying SIP functionality and performance. In addition to eliminating the need to purchase an SIP core in order to determine its in-system viability, SLE's "try before you buy" environment reduces or eliminates costly engineering iterations that often occur when a core's performance and functionality are not well-understood prior to implementation. Immediate access to meaningful information promotes a parallel rather than a sequential design process and significantly reduces design cycle times.

"SLE's SPI-4.2 model simulation environment allowed Ample Communications to complete crucial IP interoperability verification tasks very quickly and easily," said Ravinder Sajwan, CTO at Ample Communications. "Testing our internally developed SPI-4.2 in the SLE environment has allowed us to significantly reduce our product delivery time and has allowed us to prove that our products will operate successfully in our customer's systems."

"Our customers demand to know how SIP cores will work in the complex systems they are designing before they purchase them," said Mike Berry, CTO and co-founder, of SLE. "We are very pleased to be able to share our vast knowledge of SIP design and implementation with customers via SLE's model simulation environment." SLE has been licensing SPI-4 Phase 2 cores since November, 2002 and has entered into licensing agreement negotiations with more than 20 customers.

SPI-4 Phase 2 Model
First in a series of high-end interface models under development, SLE's System Packet Interface (SPI)-4 Phase 2 provides an ideal solution for packet and cell transfer in applications such as OC-192, Packet over Sonet/SDH, and 10 Gigabit Ethernet. Developed by the Optical Internetworking Forum (OIF), the SPI-4 Phase 2 standard is fast emerging as one of the most important integration standards in the history of telecommunications and data networking.

Used to accelerate data movement and reduce bottlenecks in high-speed (10 Gigabit) applications, the SPI-4 Phase 2 is being adopted by a growing number of network processor vendors and system designers who require interoperability in the 10-gigabits-per-second (Gbps) application space. Unlike similar commercially available cores, SLE's SPI-4 Phase 2 is designed entirely in "standard-cells" which facilitates cost-saving manufacturing process retargeting and the realization of critical timing requirements.

About Ample Communications
Headquartered in Fremont, Calif., Ample Communications develops highly integrated merchant silicon solutions that enable equipment vendors to achieve faster time to market with products that deliver increased speed and density and decreased power consumption and footprint. Founded in 2000, Ample is privately held and has secured $38 million in two rounds of funding. For more information visit www.amplecomm.com.

About SLE
SLE is a semiconductor design services company that provides ASIC and system technology services to the world's leading electronic systems and fabless semiconductor companies who require high-end chip design expertise. SLE's ASICBlaster solution dramatically reduces the time it takes its customers to get their products to market by offering a proven and repeatable design process, tools and semiconductor intellectual property (SIP). Founded in 1996 by former Cray Research engineers, SLE is headquartered in Eau Claire, Wisconsin. For more information, visit www.siliconlogic.com.