Attopsemi Published a Paper in ICMTS 2016, Yokohama, Japan
Hsinchu, Taiwan – May 2, 2016 – Attopsemi published a paper “Ultra-small and Ultra-reliable Innovative Fuse Scalable from 0.35um to 28nm” in 2016 International Conference on Microelectronic Test Structures (ICMTS). ICMTS was held in March 28 to 31, 2016 in Yokohama Japan and is the only conference dedicated to semiconductor test structures.
In the well-received paper, Attopsemi showed her I-fuse™, a fuse-based OTP, is programmed below a critical current. Based on collected data from 0.35um to 28nm fabricated with different materials such as WSi2, TiSi2, CoSi2, NiSi, and metal gates, the critical current is proven as the on-set of thermal run away. If a fuse is programmed below the critical current, the programming behavior is deterministic, controllable, and can be modeled precisely by physical laws as heat generation and dissipation. On the other hand, if a fuse is programmed above the critical current, as the conventional eFuse does, the programming behavior is like an explosion. The debris created after explosion can micro-bridge again and becomes shorts to cause long term reliability issues. Programmed below the critical current, I-fuse™ can easily pass the conventional 150oC HTS and 125oC HTOL for 1,000 hours, Moreover, I-fuse™ showed the OTP can pass 300oC for 4,290 hours with less than 10% of cell current changes.
Please refer to the following links for more information.
http://www.if.t.u-tokyo.ac.jp:8080/program#Memories
About Attopsemi Technology
Founded in 2010, Attopsemi Technology is dedicated to developing and licensing fuse-based One-Time Programmable (OTP) IP to all CMOS process technologies from 0.7um to 7nm and beyond with various silicided polysilicon and HKMG technologies. Attopsemi provides the best possible OTP solutions for all merits in small size, high quality, high reliability, low power, high speed, wide temperature and high data security. Attopsemi's proprietary I-fuse™ OTP technologies have been proven in numerous CMOS technologies and in several silicon foundries.
|
Related News
- Attopsemi Technology Published a Paper for the IEEE S3S Conference in October 16-19 2017, San Francisco
- Attopsemi Released White Paper "I-fuse - Most Reliable and Fully Testable OTP"
- Attopsemi Technology Attended 4th Japan SOI Symposium and Presented a Talk "I-fuse: A Disruptive OTP Technology"
- Xilinx Demonstrates 16nm Heterogeneous Multi-Processing SoC Solutions for ADAS Applications at CAR-ELE Japan 2016
- Innotech represents Cosmic Circuits in TSMC Symposium in Yokohama, Japan on 29th June 2012
Breaking News
- PUFsecurity Unveils Next-Gen Crypto Coprocessor PUFcc7 Featuring High-speed Performance and TLS 1.3 Support
- SEMIFIVE Starts Mass Production of its 14nm AI Inference SoC Platform based Product
- VeriSilicon's complete Bluetooth Low Energy IP solution is fully compliant with LE Audio specification
- TASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP
- Efabless Launches an "AI Wake Up Call" Open-Source Silicon Design Challenge
Most Popular
- Intel and Arm Team Up to Power Startups
- Chiplet Interconnect Pioneer Eliyan Closes $60 Million Series B Funding Round, Co-led by Samsung Catalyst Fund and Tiger Global Management to Address Most Pressing Challenge in Development of Generative AI Chips
- PUFsecurity Unveils Next-Gen Crypto Coprocessor PUFcc7 Featuring High-speed Performance and TLS 1.3 Support
- Renesas Introduces Industry's First General-Purpose 32-bit RISC-V MCUs with Internally Developed CPU Core
- SmartSoC Solutions Joins TSMC Design Center Alliance to Boost Semiconductor Innovation in India
E-mail This Article | Printer-Friendly Page |