Asiczen Releases its APB Verification IP
September 26, 2016 -- Asiczen Technologies announces the release of its UVM based APB verification IP. azAPB is fully compliant with AMBA APB specification. azAPB is a UVM based verification component (UVC) that can be used by IP and SOC makers to test their APB interface design effectively and quickly.
This easy-to-use UVC can be easily integrated to any UVM based environment and can be used to generate a variety of scenario without much effort. APB is designed for low bandwidth control accesses, for example register interfaces on system peripherals. This bus has an address and data phase similar to AHB, but a much reduced, low complexity signal list.
|
Related News
- Asiczen Releases its SMBus Verification IP
- Asiczen Releases its CAN Verification IP
- AMIQ EDA Releases Major Customer-Focused Product Line Update
- New Wave DV Releases Two New SOSA-Aligned 3U VPX ACAP (FPGA) Modules
- Imperas releases new updates, test suites, and functional coverage library to support the rapid growth in RISC-V Verification
Breaking News
- PUFsecurity Unveils Next-Gen Crypto Coprocessor PUFcc7 Featuring High-speed Performance and TLS 1.3 Support
- SEMIFIVE Starts Mass Production of its 14nm AI Inference SoC Platform based Product
- VeriSilicon's complete Bluetooth Low Energy IP solution is fully compliant with LE Audio specification
- TASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP
- Efabless Launches an "AI Wake Up Call" Open-Source Silicon Design Challenge
Most Popular
- Qualitas Semiconductor and Ambarella Sign Licensing Agreement
- ZeroPoint Technologies Signs Global Customer to Bring Hardware-Accelerated Compression to Hyperscale Data Centers
- Chiplet Interconnect Pioneer Eliyan Closes $60 Million Series B Funding Round, Co-led by Samsung Catalyst Fund and Tiger Global Management to Address Most Pressing Challenge in Development of Generative AI Chips
- Intel and Arm Team Up to Power Startups
- Alphawave Semi and InnoLight Collaborate to Demonstrate Low Latency Linear Pluggable Optics with PCIe 6.0® Subsystem Solution for High-Performance AI Infrastructure at OFC 2024
E-mail This Article | Printer-Friendly Page |