Synopsys Takes Hierarchical Timing Signoff Mainstream
New Automation Technology Brings 5x - 10x Reduction in Compute Costs and Runtime
MOUNTAIN VIEW, Calif., Dec. 7, 2016 -- Synopsys, Inc. (Nasdaq: SNPS) today announced 2nd generation technology that enables semiconductor design teams to adopt a smarter, more efficient hierarchical approach to static timing analysis (STA) for timing closure and signoff across all design sizes and levels of complexity. Built on proven PrimeTime® HyperScale hierarchical STA technology and included in the 2016.12 release of the PrimeTime static timing analysis tool, this new capability automates partitioning and distribution of full-chip analysis across a company's private compute cloud, reducing costs and time.
"When we brought the first generation PrimeTime HyperScale technology to our early adopters, it revolutionized the way design teams completed timing closure and signoff on the largest and most complex chips," said Robert Hoogenstryd, senior director of marketing for design analysis and signoff tools at Synopsys. "Our second generation provides additional automation and flexibility, allowing more design teams the opportunity to adopt smarter hierarchical signoff flows while maintaining the gold standard accuracy they expect from PrimeTime."
Flexible Methodology with Proven Hierarchical Technology
HyperScale has been used for static timing analysis on more than 40 of the largest and most complex designs at more than 15 different companies over the last 5 years. These tapeouts include complex graphics, high-performance computing, low-power mobile, and reliable automotive designs.
The 2nd generation of PrimeTime HyperScale technology allows users to easily migrate from flat design analysis to hierarchical block-level analysis and full-chip distributed timing analysis, using mainstream compute resources available in private computing clouds. The hierarchical methodology supports both top-down and bottom-up flows, with state-of-the-art, timing-accurate context generation. This enables HyperScale block-level model analysis to be re-used throughout the flow, instead of re-analyzing the same blocks over and over at each level. The 5x – 10x performance and memory improvements reduce both compute resource cost and schedule risk, for current and future designs.
Market-leading companies who have deployed HyperScale for use in their signoff and tapeout flows include Broadcom Limited, Juniper Networks, MediaTek, Renesas Electronics Corporation, and Samsung Electronics Company.
Availability and Resources
The HyperScale 2nd generation technology is available now as part of the PrimeTime 2016.12 release. For additional information, visit the Synopsys PrimeTime Technology page or contact your local Synopsys account team.
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software quality and security solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest quality and security, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.
|
Synopsys, Inc. Hot Verification IP
Related News
- Synopsys, TSMC and Microsoft Azure Deliver Highly Scalable Timing Signoff Flow in the Cloud
- Synopsys Speeds Timing Signoff by 2X With Latest Multicore Technology
- Synopsys Unveils Breakthrough Golden Signoff ECO Solution, Delivering 10x Productivity Improvement
- Samsung Foundry Adopts Leading Voltage-Timing Signoff Solution from Synopsys and Ansys for Advanced-Node, Energy-Efficient Chips
- Cadence Expands Collaboration with TSMC and Microsoft to Accelerate Timing Signoff for Giga-Scale Designs on the Cloud
Breaking News
- Cadence Announces Most Comprehensive True Hybrid Cloud Solution to Provide Seamless Data Access and Management
- Dolphin Design expands GoAsic partnership to enhance the semiconductor Industry's Supply Chain
- Cadence Collaborates with MemVerge to Increase Resiliency and Cost-Optimization of Long-Running High-Memory EDA Jobs on AWS Spot Instances
- M31 Successfully Validates 5nm IP Solution to Empower Global AI Applications
- Cadence Unveils Palladium Z3 and Protium X3 Systems to Usher in a New Era of Accelerated Verification, Software Development and Digital Twins
Most Popular
- Rivos Raises More Than $250M Targeting Data Analytics and Generative AI Markets
- Semiconductor Capacity Is Up, But Mind the Talent Gap
- Zhuhai Chuangfeixin: OTP IP Based on 90nm CMOS Image Sensor Process Technology Successfully Mass Production
- CMC Microsystems and AIoT Canada Sign Memorandum of Understanding to support IoT and semiconductor ecosystem growth in Canada
- Microchip Technology Acquires Neuronix AI Labs
E-mail This Article | Printer-Friendly Page |