32-Bit RISC-V Embedded Processor and Subsystem, Maps ARM M-0 to M-4. Optimal PPA,
OmniPHY Unveils 25G Backplane SerDes Silicon on TSMC 28nm Technology
Low-latency architecture paves the way for mass adoption of 100GbE Ethernet
San Jose, Calif. – March 30, 2017 – OmniPHY Inc. today announced silicon availability of its industry-leading, low-latency backplane SerDes PHY which delivers enterprise-class performance in demanding backplane applications. Developed on TSMC’s 28nm process technology based on relevant IEEE 802.3 standards, this solution meets the growing demands of data center applications, while also minimizing latency for emerging applications like financial transaction processing.
“To meet the growing demand for low-latency high-speed Ethernet, we have developed a high-performance design on a mainstream process node,” said Claude Gauthier, Chief Technology Officer of OmniPHY. “Additionally, the design is truly multi-protocol and capable of supporting several protocols from 1- to 28Gb/s. It is great to see the silicon validate our rigorous design methodologies.”
Figure 1: Transmitted 25G Eye Diagram
The industry-standard interfaces offered by OmniPHY are robust and designed to operate under harsh electrical conditions. For additional information on OmniPHY products and solutions, or to schedule a technology demonstration, please contact sales@omniphysemi.com.
About OmniPhy
Omniphy is an American mixed-signal semiconductor IP company based in San Jose, California, with satellite offices across the world. The company specializes in intellectual property and develops high-performance Ethernet PHYs and SerDes interfaces for the Automotive, Industrial, Consumer, and Networking markets. For more information visit http://omniphysemi.com or contact sales@omniphysemi.com.
|
Related News
- Omni Design Announces Silicon Validated Gigasample+ Low Power ADC and DAC on TSMC 28nm Technology
- TSMC 12FFC silicon proven SERDES Phy IPs' for HDMI 2.1, PCIe Gen5, DDR4, USB 4 & MIPI Interfaces available immediately for your next SoC
- Silicon Creations' SerDes Technology Designed into Novatek 8K TV SoC on TSMC 12nm Process
- Silicon Creations Celebrates 100th Tape-Out of Its PLL in TSMC 28nm Process Technology
- Silicon Creations Delivers 12.7G SERDES PMA for TSMC 40LP Process and PLL IP for TSMC 7nm Process
Breaking News
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
- Controversial former Arm China CEO founds RISC-V chip startup
- Fundamental Inventions Enable the Best PPA and Most Portable eFPGA/DSP/SDR/AI IP for Adaptable SoCs
- Cadence and TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
- Numem at the Design & Reuse IP SoC Silicon Valley 2024
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Qualitas Semiconductor Appoints HSRP as its Distributor for the China Markets
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
E-mail This Article | Printer-Friendly Page |