Jennic Limited's ATM SAR (Segmentation and Reassembly) technology available through IBM's Blue Logic IP Collaboration Program

Sheffield, England--October 28, 2002--Jennic Limited, a leading provider of system level digital and mixed signal Intellectual Property (IP) for system on chip (SoC), application specific integrated circuits (ASIC) and FPGA developments, has been working closely with IBM and its customers for several years and today announced that the company has joined IBM's Blue Logic IP Collaboration program. Jennic's Modular ATM Segmentation and Reassembly cores will be synthesized and optimized for IBM's Blue Logic ASIC methodology, and made available directly to IBM customers.

"Jennic's Modular ATM SAR core provides market leading performance for SoC devices requiring embedded ATM support to address the fast growing DSL and 3G market," said Jim Lindop, Jennic's CEO. "We are very pleased to collaborate with IBM in their Blue Logic program to streamline the use of Jennic's network IP portfolio with IBM's ASIC technology. We recognize that the development of Complex SoC devices in an acceptable timeframe requires a close alliance between high quality third party IP companies and silicon vendors. The team has many years experience in the design and integration of ASICs for high-speed networking, and we are delighted that this partnership will enable us to mix IBM's leading-edge processes with our technology."

"The goal of IBM's Blue Logic IP Collaboration Program is to increase the range of high quality technical solutions available to IBM's customers and enable them to meet their complex functional and time to market requirements," said Tom Reeves, vice president, ASIC product group, IBM Microelectronics. "Jennic has worked with customers on IBMs processes for several years and now, through this program, we will help to enable Jennic and other selected third party IP products to be readily licensed and integrated directly into ASICs manufactured by IBM."

About Jennic's Modular ATM SAR cores

Jennic's Modular ATM SAR cores have been designed from the outset to be efficiently embedded into low cost and high performance SoC's. The hardware-based design provides fully featured high performance ATM support while ensuring low latency and low processor overhead. The advanced traffic scheduler ensures guaranteed quality of service (QoS) is maintained simultaneously across thousands of channels. Jennic's ATM SAR is itself scaleable to support datarates from a few Mbits/second for consumer DSL applications to 622Mbits for central office and 3G basestation applications. The number of virtual channels and support for AAL5, AAL2 and AAL1 adaptation protocols can be readily configured to optimize the design for the application.

About Jennic

Jennic is a leading provider of System Level Digital and Mixed Signal Intellectual Property and silicon design services to the broadband communications market. Jennic combines its systems expertise, advanced Intellectual Property portfolios and skills in digital, software, mixed-signal and SoC design to deliver performance, cost and time-to- market advantages to its system OEMs and semiconductor customers. Jennic's Intellectual Property portfolio includes optical framers and high speed interfaces for wide and metro area networks, ATM SARs for broadband access networks and mixed signal systems based on a library of mixed-signal modules.

Jennic has completed several successful customer projects using IBMs SiGe process and has worked with IBM processes for several years. Jennic's team has also been working on the integration of access and optical networking IP this year.

Founded in 1996, Jennic is headquartered in Sheffield, England.

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