RISC-V Foundation clarifies '100 errors' reports
April 27, 2017 // By Peter Clarke, eeNews Europe
The RISC-V Foundation has commented on reports that tests performed by researchers at Princeton University had found more than 100 errors resulting from the memory consistency model of high-performance implementations of the RISC-V processor instruction specification.
Krste Asanović, chairman of the RISC-V Foundation, has published an article at the Foundation's website pointing out that although a particular RISC-V design failed over 100 tests, with reference to the C11 high-level programming language, a single change to the RISC-V instruction set architecture (ISA) specification could eliminate all these failures
The article stresses that the unmodified Rocket core did not exhibit any illegal behavior because it does not reorder memory accesses aggressively. The problematic behavior occurs when additional re-ordering is done that would be legal under the current version of RISC-V. "It is important to note that a failed litmus test does not correspond one-to-one with errors in the MCM, as a single change in the MCM could remove all litmus test failures," Asanović said in his blog.
E-mail This Article | Printer-Friendly Page |
Related News
- Interview with Rick O'Connor of RISC-V Foundation
- Imagination's new Catapult CPU is driving RISC-V device adoption
- Achronix FPGAs Add Support for Bluespec's Linux-capable RISC-V Soft Processors to Enable Scalable Processing
- Renesas Introduces Industry's First General-Purpose 32-bit RISC-V MCUs with Internally Developed CPU Core
- StarFive's RISC-V based JH-7110 intelligent vision processing platform adopted VeriSilicon's Display Processor IP
Breaking News
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
- Controversial former Arm China CEO founds RISC-V chip startup
- Fundamental Inventions Enable the Best PPA and Most Portable eFPGA/DSP/SDR/AI IP for Adaptable SoCs
- Cadence and TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
- Numem at the Design & Reuse IP SoC Silicon Valley 2024
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Qualitas Semiconductor Appoints HSRP as its Distributor for the China Markets
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process