Tensilica Standardizes on Synopsys' Physical Compiler for Xtensa Configurable Processors

Update: Cadence Completes Acquisition of Tensilica (Apr 24, 2013)

Physical Synthesis Meets the Need for High Performance Design Flow

MOUNTAIN VIEW, Calif., October 30, 2002 - Synopsys, Inc. (Nasdaq:SNPS), the technology leader for complex integrated circuit (IC) design, and Tensilica, Inc., the leader in configurable and extensible processors, today announced that Tensilica has standardized on Physical Compiler™ and developed a high performance reference flow around Physical Compiler for its Xtensa V processor cores. Tensilica now offers both a standard reference flow based on synthesis followed by place and route, and the new high performance flow using Physical Compiler. For a typical core configuration, the Physical Compiler-based high performance flow delivered a clock speed of 350 MHz in 0.13 micron technology, compared to 290 MHz achieved by the traditional reference flow. Tensilica has observed average performance improvements of 20 percent with this flow.

The Xtensa Processor Generator automatically generates customized scripts for Physical Compiler. Any changes made by the designer to extend the Xtensa processor hardware - adding instructions, registers, processor states and custom execution units - are immediately and automatically reflected in the implementation scripts for all IC implementation and verification tools supported by Tensilica, including Design Compiler™ and now Physical Compiler.

Physical Compiler, a key component of Synopsys' physical synthesis flow, enables designers to achieve the highest-performance circuits in the shortest time. By unifying synthesis and placement, it offers designers predictable, one-pass timing closure from RTL to placed gates. Built upon the market leading Design Compiler, Physical Compiler works seamlessly with Synopsys' other high-performance SoC design tools.

"Physical Compiler is an essential part of the design flow for the Xtensa-V processor," said Beatrice Fu, vice president of Engineering at Tensilica. "With our customers increasingly targeting 0.13 micron and smaller geometries, and using an ever increasing number of cores in their SoCs designs, it was imperative to augment our standard flow with Physical Compiler. We also received excellent support from Synopsys as we integrated Physical Compiler into our design environment."

"Companies such as Tensilica that are at the leading edge of core design are routinely turning to Physical Compiler to reach and exceed their original performance specifications," said Sanjiv Kaul, senior vice president and general manager, Synopsys' IC Implementation Group. "By deploying it in the high performance reference flow for its Xtensa V cores, Tensilica is ensuring that its customers have the best design technology for their complex SoC designs."

About Synopsys
Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, California, creates leading EDA tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.

Synopsys is a registered trademark of Synopsys, Inc. Design Compiler and Physical Compiler are trademarks of Synopsys. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.