Synopsys Advances Verification Platform With Next Generation Testbench Technologies
New Constraints Solver Combined With A Unified Assertion Flow Enable More Exhaustive Verification
MOUNTAIN VIEW, Calif., February 24, 2003 -- Synopsys, Inc. (Nasdaq:SNPS), the world leader in integrated circuit (IC) design software, today announced key additions to its verification platform, which enable customers to perform more exhaustive functional verification to create higher quality designs. New verification technologies include an advanced constraints solver engine for creating powerful and efficient stimulus, a new coverage engine to measure the quality of the verification environment, and support for OpenVera™ Assertions (OVA) to provide a unified platform for assertion-based verification methodology. These technologies have been added to the latest release of the Vera® testbench automation tool and work seamlessly with the VCS™ 7.0 HDL simulator to address the increasing system-on-chip (SoC) functional verification challenges.
"Synopsys is setting the standard in next generation constrained-random methodology and assertion-based verification flow," said Manoj Gandhi, senior vice president and general manager of the Verification Technology Group at Synopsys. "Our customers are already using the advanced algorithms in the new Vera constraints solver to address their critical verification challenges. Native support of assertions in VCS and Vera, combined with Vera's powerful stimulus generation capabilities, provides a powerful verification platform enabling higher productivity."
The new constraints solver in Vera is flexible and powerful, enabling users to implement a highly efficient constraints-driven random verification methodology. The new solver uses formal techniques and multiple engines to provide unprecedented power to solve highly complex constraints. Users can quickly get solutions for hundreds of simultaneous constraints, each with hundreds of random variables. The new solver enables users to more exhaustively simulate a design's functionality, including corner-case scenarios, resulting in greater confidence in the design quality. Additionally, this engine is architected for compatibility with the constraints language that is being defined for Accellera's emerging SystemVerilog standard. "Our verification methodology is based on constraint-driven random stimulus generation," said Amir Freizeit, vice president of research and development at Emblaze Semiconductor. "Emblaze Semiconductor is a leading fabless integrated circuit company, providing comprehensive and customized semiconductor-based solutions for high volume multimedia appliances in the telecommunications, consumer and security markets. The complexity of our designs requires that we write and solve a large number of complex constraints. After an in-depth study of all the solutions available in the marketplace, we have standardized on Vera for our testbench needs. The new constraints solver was able to quickly solve more than 500 simultaneous constraints, each with more than 200 random variables, with minimum memory consumption."
Vera features a new powerful and flexible functional coverage engine that, combined with the new constraints solver, enables engineers to create highly efficient tests and eliminate redundancy from the verification environment. The new engine supports coverage accumulation and grading from regression runs and shares a common database format with VCS' built-in code coverage engine.
"Synopsys' verification platform provided us with a powerful verification environment," said Lynne Brocco, vice president of hardware engineering at StarGen, Inc. "The new constraints solver engine in Vera, combined with the built-in coverage analysis in VCS, raised verification productivity and created higher quality designs for our StarFabric switched interconnect technology."
The latest release of Vera and VCS supports OpenVera Assertions (OVA) to provide a unified platform for assertion-based verification. The unified platform increases productivity and enables assertions reuse throughout the verification process to detect design bugs faster. Availability
The latest release of Vera (version 6.0) is available now. VCS (version 7.0) with native support of OVA is also available now.
Synopsys Verification Platform
Synopsys' verification platform supports Verilog, VHDL, mixed-HDL, and mixed-signal simulation for complex SoC designs. Aimed at achieving the highest verification productivity, the verification platform includes Synopsys' VCS HDL simulator, CoCentric® System Studio for SystemC™ simulation, Vera® testbench automation tool, VCS-NanoSim™ package and HSPICE for mixed-signal simulation, and Formality® equivalence checker.
Synopsys, Inc. (Nasdaq:SNPS) is the world leader in electronic design automation (EDA) software for integrated circuit (IC) design. The company delivers technology-leading IC design and verification platforms to the global electronics market, enabling the development of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and is located in more than 60 offices throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/.
Synopsys, Vera, CoCentric System Studio and Formality are registered trademarks of Synopsys, Inc. VCS, NanoSim and OpenVera are trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
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