ARC licenses processor for digital imaging systems to Conexant

ARC had won the original Raptor II design slot as a result of the ease with which its user-customizable, 32-bit microprocessor could be designed in, according to the companies. The integration of the processor into the chip was completed by Conexant's ASIC design team in five days.

The Raptor II includes the Raptor II advanced SIMD DSP image processing engine and ARC's core. It controls virtually all functions of a digital camera including motors, USB, IrDa, ATA controllers, NTSC/PAL/LCD or direct digital displays that would normally require additional external control logic, the companies said. For more information visit www.arccores.com.

---

MoSys Inc. (Sunnyvale, Calif.) has unveiled a family of standard 1T-SRAM memory macros using what it claims to be silicon-proven 0.25-micron and 0.18-micron cores.

With this extension to MoSys' current offering of custom-designed embedded memory products, customers have the added convenience of off-the-shelf 1T-SRAM memory macros in common sizes and configurations for rapid integration into their products.

The standard cores are available in 1- and 2-Mbit sizes and both high-speed and low-power configurations. Customers can also select from different memory bus widths as well as read and write timing interfaces, delivering the high-density advantages of custom 1T-SRAM macro design with the time-to-market advantages normally only possible for compiled macros. A total of 36 different macro configurations are available.

Mosys is licensing these standard macros on a low-cost, single-project-use basis but will allow customers to use multiple instances in their designs to achieve larger on-chip memories.

The deliverables of the macro kits include a data sheet, simulation models, timing model, layout phantoms, GDSII database and test documentation.

Pricing for MoSys' 1T-SRAM standard macros starts at $100,000. Further information is available at www.mosys.com.

---

Design and Reuse, in cooperation with IFIP WG10.5 and INPG, will offer its workshop, IP-Based Design'2001, in Grenoble, France, on Dec. 5-7. The workshop will examine "hot topics on design and CAD" and will look at intellectual-property-based system design, IP/system-on-chip qualification, IP/SoC prototyping, IP/SoC modeling and internet technologies for IP exchange.

In particular, the show will include sessions on hard IP, IP migration, submicron technology issues, IP/SoC modeling and socketization, design platforms, IP/SoC qualification, prototyping methodologies and platforms, reusability assessment, IP exchange technology, and IP/SoC database and catalog technology.

Organizers said the workshop will include a mix of technical papers, panels and presentations with a balanced contribution from industry and academia. The organizers are currently seeking papers. The deadline for manuscripts is Sept. 17. Persons submitting papers will receive notification of acceptance by Oct. 19.

For more information, visit www.us.design-reuse.com/WORKSHOP/submit.html.