NEC makes serious push for ASIC-lite

Designers that choose to develop custom chips using ISSP sacrifice some speed and power consumption for a less-burdensome ASIC design methodology based on predefined memory, intellectual property and test structures. User-defined logic is implemented in the upper two metal layers of the chip. NEC claims it has designed 22 chips based on ISSP since the platform was introduced i n 2001.

Design houses are among those NEC wants to enlist. The company is talking to GDA Technologies Inc. (San Jose, Calif.), CoreSim (Kanata, Ontario) and a handful of Japanese companies to oversee front-end synthesis and pre-layout work, which would then be handed off to NEC for layout and verification. Later, NEC would like to have some of these partners do the entire design, including the back end, said Phil LoPresti, general manager of the custom LSI business unit of NEC Electronics America.

"Ultimately, we're going to have our own dedicated staff to do the back-end process," LoPresti said.

This is part of NEC's plan to draw more designers to the ISSP platform, which targets chips that will ship in unit volumes of 100,000 or less. If the platform succeeds in attracting a fair number of designers who would otherwise have chosen an FPGA, NEC believes it will need more capacity to service them without having to drastically increase its head count, LoPresti said.

One way NEC is trying to persuade engineers to switch to its structured ASICs is by giving them a way to convert FPGA designs to the platform. Today, there are no set guidelines on how to do so, but NEC says it is working with electronic design automation partners to develop some.

NEC plans to come up with a migration path "that is more formal and takes away more of the headaches from the customer so that we can do a kind of turnkey conversion," said Chung Ho, director of NEC's U.S. custom-LSI business unit.

NEC is also trying to get IP vendors on board by opening the ISSP design environment and offering the vendors a less costly way to verify their IP in silicon via multiproject wafer runs, which lets several companies share the cost of making a mask. Comm-centric IP provider Modelware Inc. (Red Bank, N.J.) is the first to publicly sign on.

Another way NEC hopes to draw more designers to its ISSP platform is by putting it on the technology fast track. This week, the company is announcing plans to offer its next-generation ISSP based on 90-nm process technology. Users can select from a master lineup of four devices that contain between 1 million and 4 million usable gates and from 1 Mbit to 10 Mbits of SRAM. The chips can run at a maximum frequency of 500 MHz.

In addition, ISSP2 has three new IP cores that were not a part of the previous offering: a 10-Gbit/second serializer/deserializer; a 3-Gbit/s serial AT bus attachment interface; and a 10-Gbit Ethernet MAC. NEC said the libraries for the ISSP2 will be available next January, with production expected to start in April 2004.

Compared with standard-cell design, ISSP2 will continue to take about a 10 to 15 percent hit on performance while

The message resonates with the business managers of customers, and NEC hopes it will do the same for customers' understaffed engineering teams. "They don't have the volume or the design teams or the ability to buy all the tools that they did in the past," LoPresti said.