Embedded SRAM test and repair moves on-chip

Embedded SRAM test and repair moves on-chip
By Anthony Cataldo, EE Times
July 11, 2001 (2:15 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010711S0058

SAN MATEO, Calif. — With the rollout of its Star Memory System, an on-chip test and repair mechanism for embedded SRAM, memory compiler specialist Virage Logic Corp. is making good on its promise to provide a way for chip companies to shuck their back-end memory testers.

Virage is also touting big savings by enabling higher wafer yields earlier in the ramp of a new chip design. In one case, the company claims it helped a customer save nearly $27 million in the first year of production through higher yields, lower test costs and faster time-to-market.

Virage claims the test and repair algorithm, which comes in the form of hardwired logic gates, will fix as much as 99 percent of the bad bits in an SRAM design embedded into a larger system-on-chip implementation.

The test and repair logic takes advantage of redundant rows and columns of memory that the company has been generating with existing compilers. But rather than using lasers to br eak fuses to open up the extra memory bits and then run the devices through back-end memory testers, the memory subsystem can test, repair and allocate redundant bits automatically on-chip.

To do so, Virage has augmented its SRAM compiler to generate a hardwired test and repair algorithm that takes anywhere from 5,000 to 7,000 gates, as well as a fuse box and interfaces to SRAM and external logic testers.

There are four components of the test and repair logic: a foundry-specific built-in self-test algorithm; built-in self-diagnostics that give feedback to the foundry to help improve memory process yields; repair and redundancy allocation logic; and an algorithm for reconfiguring the rows and columns to be topologically efficient.

There are three versions of the "Star processor" test and repair logic: two for single-port memories and one for dual-port designs. Virage chose this approach to avoid the extra routing die-area penalty that would have been incurred had only one logic block been used.

For example, one of Virage's early customers that is using the test and repair scheme is using one Star processor for four memory blocks and another algorithm for a separate SRAM block. "Having a second processor actually made it smaller, because to route all the signals across the chip with one array would have caused an increase in the physical layout of the chip," said Vincent Ratford, vice president of business development for Virage (Fremont, Calif.).

When failures are detected, a repair signature is loaded into the fuse box, which displaces the external laser used to open up the extra bits. The fuse box is small enough to be placed almost anywhere on the chip.

To interface to the test and repair logic, the memory itself is given a "wrapper," which contains the address generators, data generators and comparators. The wrapper and redundant bits add another 3 percent of die area to the memory array.

There's a seven-wire P1500 interface to connect to an 1149.1 interface, which is used for lo gic testing. This obviates the need for an extra memory tester or more-sophisticated testers that perform logic and memory tests. "Most [test houses] have logic testers but they don't have memory testers, and their logic testers don't have memory test options," Ratford said.

The memory test and repair subsystem starts at $170,000; per-unit royalties are also applicable. Virage says it can deliver the register transfer level code to customers three weeks after receiving an order. Under its licensing contract, Virage will assume responsibility for the yield of the memory subsystem, Ratford said.