Net processors seen morphing into SoC

Net processors seen morphing into SoC
By Craig Matsumoto, EE Times
July 12, 2001 (1:02 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010711S0059

SAN MATEO, Calif. — The network processor game has barely begun, but at least one company is calling the ending already, espousing a future in which NPUs and coprocessors, boiled down to intellectual-property cores, are knitted onto massive systems-on-chip (SoCs).

Officials at Clearwater Networks Inc. say that even their choice of niche — a Layer 4 through 7 adjunct to a packet-forwarding engine — came from the Los Gatos, Calif., company's belief that network processors will be subsumed into systems-on-chip. The theory is that packet processors and classifiers will become standard parts, and that both ultimately will be integrated in order to lower costs and avoid the delays of sending signals off-chip.

"People will stop talking about the classification market and the [packet] forwarding market. It'll be the classification cell and the forwarding cell," chief executive Dan O'Neill s aid in a recent interview with EE Times.

From the start, Clearwater's strategy was to design its "services" processor to be the programmable element on an SoC network processing unit, O'Neill said. Everything in the design followed that philosophy: The company used the MIPS instruction set for compatibility with customers' existing code, and it stuck to less advanced processors and a humdrum CMOS process in order to better its chances of integrating with other NPU-related cores.

"Our objective is to take this core [the Clearwater chip] and integrate it with different peripheral blocks. So we want it to be as abstracted from the design process as possible," O'Neill said. "If I push clock speed, then I have to get down to the physical layer."

O'Neill believes the push for an NPU SoC will be driven by the need for access and metropolitan networks to adjust to OC-768 speeds. Initial OC-768 deployments in the network core won't need complex packet processing, because core switches are asked onl y to provide raw speed. But as OC-768 speeds creep toward the edge, network processors and related devices will need to find ways to keep up, prompting a need for silicon integration, he said.

While many functions related to network processing will no doubt boil down to intellectual-property (IP) cores, a monolithic system-on-chip containing all of them isn't likely to appear soon, said Bob Merritt, an analyst with Semico Research Corp. (Scottsdale, Ariz.). The problem lies in the number of functions required of such a chip, including packet forwarding, classification and queue management.

"The amount of silicon to accomplish all that is going to increase, not decrease," Merritt said. "As long as we're in an environment where silicon is increasing, that concept [the SoC] doesn't hold together."

In fact, existing single-chip network processors won't handle next-generation requirements without the added help of external coprocessors, Merritt said. "I don't see us reaching the outer boundaries of what routers and switches are doing in the near future."

Some NPU vendors added that the SoC tends to be a tough nut to crack. "I spent a lot of time at Intel, where we tried to do integrated chips many times and failed many times," said Mitch Kahn, vice president of marketing for Silicon Access Networks (San Jose, Calif.). "You just can't get the performance you need using an integrated solution."

Analyst Merritt agreed that Clearwater's plan may prove viable in the very long run, however, if data rates level off and router requirements begin to stabilize. "Then you're in an environment like PCs, where the total silicon [area] starts to shrink," he said.

And he endorsed Clearwater's contention that certain functions can be reduced to IP cores and combined on ASICs. "I agree with that part of their solution, but I don't believe the total amount of IP will be able to reduce itself to a single piece of silicon," Merritt said.

Breakup theory

Al ternatively, it's also possible that individual functions will have to be broken up separately, a theory espoused by Bhanu Nanduri, vice president of marketing and business development for chip vendor Lara Networks Inc. (San Jose). "We expect the NPU to gravitate to a set of specialty processors" at OC-192, he said. "I expect these functions to all be broken up." Companies such as Azanda Network Devices (Sunnyvale, Calif.), ZettaCom Inc. (Santa Clara, Calif.) and Silicon Access are working along those lines. "Certain [market] segments will need an integrated solution. Some of the other [markets] will need a chip set," Nanduri said.

Officials at Silicon Access believe that customers will want to shop around for NPUs, coprocessors and switch fabrics, a scenario that chief executive Perry Constantine thinks will preclude SoC development. "You have to give the customer the ability to architect his solution instead of architecting it for him," he said.

But Clearwater's O'Neill says his SoC prediction is a reflection of ongoing trends.

"It's almost always the case that the programmable engine has been the king of the board, because that's where the software resides," O'Neill said.