Tensilica navigates 'sea of processors' designs

Tensilica navigates 'sea of processors' designs
By Chris Edwards, EE Times UK
June 14, 2001 (8:00 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010614S0057

LONDON — Tensilica Inc., a developer of configurable processor cores, has developed a multiprocessing extension to its architecture that Chris Rowen, chief executive officer, sees as a new generation of "sea-of-processors" designs.

Rowen unveiled the direction the company was taking in a panel at last year's Design Automation Conference in Los Angeles. Less than a week before this year's event in Las Vegas, the company took the wraps off its Xtensa IV core at the Emebedded Processor Forum in San Jose, Calif.

The company has avoided building a core for symmetric multiprocessing — the direction now being taken by processor core vendors such as ARM and MIPS.

Instead, Tensilica is focusing on an environment where processors designed to perform a small number of specialized tasks would be coupled tightly and used as replacements for hardwired or microsequenced logic.

Dan Fraley, senior vice president of engineering at Hughes Network Systems, said his company would use a number of Xtensas in its Spaceway satellite communications network equipment to handle specific tasks. Another Xtensa running a real-time operating systems would act as a control processor.

The main change made for the Xtensa IV is a new memory interface to tie together multiple instances of the core in dataflow-style environments, together with hardwired state machines.

The bus can be up to 128 bits wide for a peak bandwidth of 3.2 Gbytes/second.

The debug interface has also been changed to allow a daisy-chained arrangement where developers can monitor and debug software on a number of processors using selective breakpoints.

To model arrays of processors, the company is using a programming interface for system modelling. Through this, a simulation of multiple C processors can be used to weigh up different architectures and decide how best to perform load balancing.

For use as a host processor, the company has added a memory management unit (MMU) opt ion with translation lookaside buffers (TLBs) to cache information about virtual-memory pages. The MMU can have separate data and instruction TLBs.

Chris Edwards is the editor of Electronics Times, EE Times' sister publication in the United Kingdom.