Fujitsu hurries 90-nm structured ASIC

Fujitsu hurries 90-nm structured ASIC
By Ron Wilson, EE Times
September 9, 2003 (8:07 p.m. EST)
URL: http://www.eetimes.com/story/OEG20030909S0030

SAN JOSE, Calif. — Taking a different tack from its competitors in the structured ASIC market, Fujitsu Microelectronics America, Inc. (Sunnyvale, Calif.) said Tuesday (Sept. 9) it plans to bring 90 nm and direct-write e-beam technology to bear on the market in 2004.

Far from seeing the market as a time-to-market play for mid-range and low-end ASIC designs — and hence a defensive move against FPGAs — Fujitsu sees the technology as a primary delivery vehicle for advanced ASIC processes.

"We expect to release the first 90-nm AccelArray family in the first quarter of 2004," said Vincent Shen, senior director of ASIC engineering at Fujitsu. "We believe that the AccelArray, which eliminates many of the back-end design steps for customers, will be an excellent way of offering customers the benefits of 90-nm technology without exposing them to the complexities of being an early adopter of a challenging process."

On this schedule, the first 90-nm AccelArray product will be available just a few months after the first external customer tapeout on Fujitsu's 90-nm process. That is now scheduled for a U.S. foundry customer for later this month or early October.

That compares to the delay of a year or more that has typically separated the release of a gate-array family from the release of the underlying process to advanced COT design teams.

The first 90-nm AccelArray is expected to be a general purpose device much like the existing 130-nm AccelArray MegaFrame chips. Not far behind, however, will be the first in Fujitsu's line of more application-directed AccelArrays. The device will have a large number of instances of Fujitsu's diffused serdes and universal PHY macros, providing as many as 32 high-speed serial channels.

The AccelArray devices, like other structured ASICs, are built on a base wafer that includes configurable I/O cells, metal-configured logic cells and memory blocks. Power and clock distribution and test circuitry are also pre-defined, as are analog PLLs.

Customers will hand off a verified net list or RTL design to Fujitsu, which will then perform back-end design — mapping the net list onto the array elements and creating the three metal layers that characterize the elements, configure the memories and establish the user-defined interconnect.

Shen said the back-end process at Fujitsu takes from two to four weeks, with perhaps another week for synthesis if the customers chooses to hand off at RTL. Approximately one month after the customer signs off on the returned timing, Fujitsu can deliver sample chips.

This represents a six- to eight-week turnaround for 90-nm chips, according to the company, in exchange for some sacrifice in maximum speed and density. "Let us just say that the largest AccelArray today in 130 nm offers about 3.5 million user gates," Shen said. "We feel that is too small for some of our customers, so we are enlarging it in the 90-nm process."

Another major technology move will shrin k the turnaround time for samples even further. In mid-2004 Fujitsu intends to begin using direct-to-wafer e-beam technology to pattern the three user-defined metal layers, eliminating the process of making masks for those three layers for prototype chips. This could potentially reduce the time from timing sign-off to sample dice to two weeks, Shen said.

"We have used the e-beam equipment for other purposes on earlier process generations, so the equipment is there and ready to go," he explained.