Dual MIPS processor runs at 1 GHz

Dual MIPS processor runs at 1 GHz
By Chris Edwards, EE Times
June 13, 2001 (5:42 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010613S0073

LONDON — PMC-Sierra Inc. this week described a high-performance dual-processor device based on the MIPS 64-bit architecture. Like many other processors described at the Embedded Processor Forum, it is aimed at communications applications.

PMC-Sierra (Burnaby, British Columbia), known as a supplier of fixed-function communication cores, last year acquired QED Inc., a developer of MIPS architecture implementations. That acquisition has yielded the 1-GHz RM9000x2 dual processor, which draws about 5 watts in a 0.13-micron implementation built by Taiwan Semiconductor Manufacturing Co. Ltd. The device is aimed at high order packet processing and routing in applications such as OC-192 supporting 10-Gbit/second transfers.

The company has developed a memory hierarchy for the RM9000x2 that aims to reduce the bandwidth the two processors consume on the chip's shared buses. To deal with faster packet interfaces, designers have built a migration path f rom the classic MIPS bus to the HyperTransport scheme championed by Advanced Micro Devices Inc.

PMC-Sierra has opted to use a modified-shared state protocol with two 256-kbyte Level 2 caches, said Andy Keane, vice president of marketing for the MIPS processor division of PMC-Sierra. "The modified-shared state allows shared data that is dirty to remain in the cache. Without this state, any shared [cache] line would be written back to memory to change the state. Since we have a dedicated fast path from CPU to CPU, this state maximizes the use of this path rather than the path to memory, which is inherently slower.

"This state makes packet pipelining more efficient," Keane said. "If you do one set of operations, such as parsing, on one CPU and then pass the packet to the other for modification, the modified-shared state lets you pass packet information through the caches rather than through memory."

To speed up the passing of packet data to the processor, the Level 2 cache can be bypassed when data is loaded directly into the 16-kbyte Level 1 cache attached to each processor.

To get to the 1-GHz clock speed, designers extended the pipeline in the MIPS64-compatible processor to seven stages. To reduce the impact of branches on the longer pipeline, the RM9000x2 uses a branch-prediction scheme called Gshare.

The two processors on the RM9000x2 have access to four ports for memory and I/O through a shared memory fabric. One is a low-speed interface to control-plane processors. The others implement a 200-MHz double-data-rate memory interface and two I/O ports, based on an updated version of the MIPS SysAD bus and AMD's HyperTransport link.

The shared memory fabric allows concurrent transfers between ports and contains 16 entries of 32 bytes each to minimize contention for access to each of the ports.

PMC-Sierra decided to support both SysAD and HyperTransport to take advantage of existing networking peripherals for MIPS-family processors and move forward to the faster 500-MHz HSTL interfaces used by HyperTransport.

"HyperTransport is derived from packet-style buses, which matches the type of data we most commonly process," Keane said. "Since all code and data is resident off a separate port to main memory, the most common type of data [passed] through HyperTransport will be packet information.

"HyperTransport also uses a differential signalling strategy that decouples the I/O clock from the CPU and is inherently more immune to noise than old-style single-rail buses," he said. "HyperTransport uses fewer pins. With an 8-bit data path in and an 8-bit data path out, both driven at 500 MHz, we can achieve 2 Gbytes/second of bandwidth on a bus that consumes 40 signal pins.

"Compare that with a 64-bit SysAD that consumes over 80 pins for a similar function and less bandwidth. At 125 MHz, SysAD tops out at 1 Gbyte/second. HyperTransport starts at 1 Gbyte/second and will scale above a 1-GHz clock rate, or 4-Gbyte/second transfer rate. With fewer pins, we can also add additional HyperTransport channels."

The chip will run from three different power supplies. The core will run at 1.2 V, the DDR interface at 2.5 V and the SysAD and local control buses at 3.3 V. PMC-Sierra expects samples by the end of the year.

Chris Edwards is editor of Electronics Times, EE Times' sister publication in the United Kingdom.

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