MIPS Technologies Boosts System Performance Through New Multi Threading Extensions to MIPS® Architecture

Only MIPS Technologies Offers Complete Solutions to SOC Designers, Including High Performance, Programmability and Multi-Processing

SAN JOSE, Calif, Microprocessor Forum - October 13, 2003 - MIPS Technologies, Inc. (Nasdaq: MIPS, MIPSB), today announced the MIPS® MT ASE (Application Specific Extension), a new multi-threading extension to its industry-standard architecture. Now, SOC designers are able to significantly increase delivered system performance through higher processor efficiency in applications that can take advantage of a multi-tasking approach to SOC design. Additionally, dedicated IP (such as DSPs) can be eliminated, lowering system costs by migrating more independent functions onto a single MT enabled MIPS-based™ core. The MIPS MT ASE is tailored toward silicon companies doing MIPS-based designs, and makes the MIPS32™ and MIPS64® architectures the only ones within the embedded industry to offer a full spectrum of solutions for SOC customers.

Today's feature-rich devices are incorporating more and more functionality to deliver an enhanced user experience. However, traditional single processor approaches cannot take advantage of the inherent parallelism these applications exhibit, such as parallel data operations to process audio and video algorithms, and shared multi-tasking compute environments. This trend is forcing semiconductor companies to exploit techniques such as multi-threading to increase overall system performance by enabling processors to share unused CPU resources across multiple threads of data. The result is increased processor efficiency: concurrent data streams run in less time, and/or the same amount of work can be done on a smaller number of processors.

"The introduction of multithreading to the well-known MIPS architecture is nothing less than the beginning of a new dynasty for multithreading RISC processors," said Jim Turley, technology analyst and editor of the Silicon Insider. "This is a big milestone in the twenty-year history of important advancements to the MIPS architecture. It adds a whole new set of features to MIPS-based designs that could potentially enable new types of applications."

"Multithreading squeezes more performance out of the same number of clock cycles to deliver greater processor efficiency," stated Tony Massimini, chief technology officer of Semico Research. "At the same time, companies can reduce die area and, therefore, overall costs and power consumption of their design. The bonus benefit, of course, is that this solution is based on an industry-standard architecture that enables users to tap into broad third-party software support for fast adoption."

"The MIPS multi-threading ASE is the next step toward helping our customers realize a greater level of silicon efficiency and cost effectiveness on an industry-standard architecture," said Victor Peng, vice president of engineering for MIPS Technologies. "This new architectural extension adds to our broad range of IP solutions, such as the M4K core, that customers can use for single-chip multi-processing SOCs."

The MIPS MT ASE
The MIPS MT ASE brings multi-threading to an industry-standard architecture, enabling customers doing embedded multi-tasking designs to protect future investments and leverage the broad range of hardware and software support for the MIPS architecture. Uniquely, the MIPS MT ASE incorporates two levels of multi-threading capability:

• Virtual Processing Elements. This feature enables two virtual processors to share common resources, while still appearing to be independent cores to the software base. This software transparency protects existing investments in operating systems and applications, yet allows a second virtual processor to run an independent thread delivering increased processor efficiency.
  
  
• Fine grain threading. Using new instructions added to the MIPS32 and MIPS64 architectures, fine grain threading enables applications using MIPS MT ASE instructions to exploit inherent application parallelism. Processors designed to take advantage of these instructions can, in simple RISC operations, spawn and control independent threads that share existing hardware. These threads are then scheduled dynamically by hardware, dramatically raising processing efficiency.

The MIPS MT ASE also incorporates "QoS" or Quality of Service scheduling. This capability allows one or more real-time threads of execution to be allocated to a defined portion of the total compute power of a multi-threaded processor. Applying MIPS MT ASE QoS scheduling to MIPS-based CPUs enhanced with the CorExtend function for intensive media processing, solves major real-time scheduling problems of DSP-enhanced RISC processors.

Features of the MIPS MT ASE

	Scalable architecture
	Applicable to large and small cores Improves processor efficiency  -Memory, I/O, or any other long latency can be hidden  -No context save or set-up on an interrupt or exception

	Leverages software investment
	Provides a standard framework for multi-threaded architecture  -System coprocessor interfaces to manage new resources  -Compatible with existing SMP software Provides standard instruction set semantics to manage concurrency  -Supports finest possible grain of control parallelism  -Allows thread migration in multi-core designs

	Leverages software investment
	Provides a standard framework for multi-threaded architecture  -System coprocessor interfaces to manage new resources  -Compatible with existing SMP software Provides standard instruction set semantics to manage concurrency  -Supports finest possible grain of control parallelism  -Allows thread migration in multi-core designs

	Flexible thread scheduling
	Supports multiple algorithms  -Blocking, TDMA, simultaneous multi-threading, hardware-based swapping Separates real-time/DSP and interactive scheduling domains for performance guarantees

	Thread migration
	Threads are relocatable in multi-core systems

	Virtual resource pool
	Applications and OSs see a large "virtual" thread resource pool, since thread context is software visible

	Low cost implementation
	Designed for low implementation overhead

Application Examples
Using a MIPS32 24Kc™ core, an SOC designer can reduce silicon real estate by as much as 46 percent when compared to a multi-core solution. For example, in a video decompression engine the application can be split across multiple cores, each processing a video segment. The inherent data parallelism of this application is leveraged by the processors delivering increased system performance. Multi-threading allows the same or better performance with the 46 percent silicon area savings, preserving the SMP software model.

In today's SOCs, control plane functions are separated from data plane functions as the latter require known latencies and performance characteristics that are difficult to generate when shared by a common processor. The MIPS MT ASE allows guaranteed allocation of processor bandwidth to specific tasks, where in the case of a merged control and data plane, it is possible to guarantee 75 percent of the processor cycles to the data task, while allowing the less time-critical control plane functions to fill the remaining time.

Availability
The MIPS MT ASE will be available for licensing by MIPS32 and MIPS64 ISA customers. Additionally, this technology will appear in future 32- and 64-bit cores developed by MIPS Technologies.

About MIPS Technologies
MIPS Technologies, Inc. is a leading provider of industry-standard processor architectures and cores for digital consumer and business applications. The company drives the broadest architectural alliance that is delivering 32- and 64-bit embedded RISC solutions. The company licenses its intellectual property to semiconductor companies, ASIC developers and system OEMs. MIPS Technologies and its licensees offer the widest range of robust, scalable processors in standard, custom, semi-custom and application-specific products. The company is based in Mountain View, Calif., and can be reached at +1 (650) 567-5000 or www.mips.com.