SANTA CLARA, Calif. -- NEC Corp.'s microprocessor operation here today announced major enhancements to its embedded 64-bit RISC processor platform, adding a deeper pipeline architecture and out-of-order execution capabilities. The enhancements will enable the 64-bit processors to deliver up to 1,600 million instructions per second (MIPS), while operating at speeds up to 800 MHz in the next couple years, said the company.
NEC Electronics' new VR5500 processor series is based on the 64-bit RISC architecture from MIPS Technologies Inc. and targeted at a range of embedded applications in consumer digital devices, set-top boxes, thin-client networking systems, and Internet appliances, said product managers. NEC also today announced a new software-configurable system controller, the VRC5477, for the processor series to act as a memory controller and bus host bridge in embedded systems.
The initial VR5500 processors will be available this year wit h 600 MIPS performance at 300 MHz. The embedded MPU series will scale up to 400-MHz in 2002 and the 600-to-800 MHz range in 2003, said Karl Auker, assistant general manager for the VR Microprocessor Strategic Business Unit at NEC Electronics. The architectural enhancements enable the 64-bit processors to deliver a two Dhrystone MIPs for every clock cycle at the higher speeds.
A key feature in the processor is a new dual-issue out-of-order superscalar design, which uses a 10-stage decoupled superpipeline, said NEC managers. "We have deepen the pipeline so that it is scalable for much higher frequencies, and the out-of-order execution capability allows the processor to offset latency issues normally associated with moving processors to higher speeds," Auker said.
The VR5500 has also been given a modular execution unit design that will allow additional processing units to be added to the core, he said. The core can be given a second floating-point unit, for example, or specialized functions for multime dia and digital signal processing. The core contains two 64-bit arithmetic logic units (ALUs).
The VR5500 pipeline structure is organized in three blocks--in-order fetch, out-of-order execution, and in-order commit pipelines. The out-of-order pipeline enables the processor to continue executions regardless of delays in fetching operations memory. "Latency won't stall the processor," Auker told SBN.
NEC Electronics is planning to increase the speed of the VR5500 to the 400-450 MHz range with samples being available early next year. These parts, like the current VR5500, will be fabricated with a 0.13-micron process and operate with a 1.5-V core. In the second half of 2002, NEC will introduce a VR7700 series with a level two cache and double data rate (DDR) memory interface. A new 0.10-micron copper chip process technology will be applied to this series in 2003 to take the processor speeds up to 600-to-800-MHz.
"The VR5500 is the beginning of our future technology in the 64-bit MIPS area. We will be focusing the core on standard processors and integrated parts for customer applications," Auker said.
Samples of the first VR5500 are scheduled to be available in the third quarter of 2001, packaged in a 272-contact ball-grid array (BGA). NEC said it is planning to price the processor at $35 each in 10,000-piece quantities.
--J. Robert Lineback