Verisity's Verification Viewport Strategy to Broaden Process Automation Scope
Direction will Link Hardware Designers, Software Developers, Verification Specialists, Architects and Project Managers
MOUNTAIN VIEW, CA November 17, 2003 Verisity Ltd. (Nasdaq:VRST), today announced a broad reaching strategy to provide specialized views for all stakeholders in the verification process. Another major component of its Verification Process Automation (VPA) mission, Verisity's strategy will provide Verification Viewports to each specialist in the design and verification team, including hardware designers, software developers, verification specialists, architects and project managers. These viewports will integrate each stakeholder into a complete project-wide flow that yields optimal productivity, quality, predictability and resource utilization. In addition, Verisity's Verification Viewports strategy will expand Verisity's support of evolving industry standards and breadth of system and project-level analyses.
Verisity's VPA solutions automate the process that starts with executable specs and verification plans to the realization of 'total coverage' of hardware and software functionality and verification closure. Today, Verisity's VPA solutions enable verification specialists to create verification environments for systems or ICs. The design itself can be modeled in any of the common languages, including Verilog, VHDL, SystemC, e, PSL, OVL and SystemVerilog for modeling hardware; and C, C++, or assembly language for software. Designs can also be accelerated or emulated in hardware. As the verification complexity continues to explode, each engineer has new needs and requires new inputs to the verification process and environment. As each of these specialists continue to use different languages for design, and have different perspectives on what they need to verify, it is critical to provide project teams with multiple specialized, optimized viewports for verification. This motivation was also behind Verisity's recent proposal to converge a more concise IEEE 1364 '05 Verilog standard proposal with Accellera's SystemVerilog, while complementing the emerging IEEE P1647 HVL standardization effort based on e.
"Verisity's Viewport strategy makes a lot of sense for customers who want off-the-shelf advanced verification solutions to complement the Cadence® Incisive verification platform," said Paul Estrada, vice president of strategy and market development at Cadence Design Systems. "By working together through the Cadence Connections® Program, Cadence and Verisity are ensuring that architects, designers, verification engineers and software engineers get optimal solutions for their toughest verification needs. We are also making our tools work together to provide multi-language solutions based on standards such as VHDL, IEEE 1364 Verilog, SystemVerilog, SystemC, PSL, and IEEE P1647 based on e."
Verisity's Verification Viewports will include:
a) Verification Specialist Viewport: enables projects to move from executable verification plans to module, unit and chip/system level 'total coverage' and verification closure. This viewport was designed to work across both hardware and embedded software domains, and across all forms of simulation and hardware-based modeling infrastructure. The Verification Specialist Viewport supports the e verification language, the foundation of the emerging IEEE P1647 standard, executable verification plans, verification management, total coverage analysis, failure analysis, sequence and signal-level analyses, access to a large verification IP repository and parameterized verification component and environment interfaces.
b) Architect's Viewport: will provide architects with multiple ways to access system scenarios, traffic generation technology and analyses, for system functionality and performance verification. This viewport will support C, C++, SystemC, and e with sequence-level abstractions, parameterized interfaces of existing verification environments and sequence-level visualization and analyses.
c) Hardware Designer Viewport: will enable module-level verification and 'design for verification' with embedding of assertions and coverage points. This also includes Verisity's recently announced Coverage and Assertion Interface (CAI) in support of open assertion standards such as PSL, OVL and SVA assertions. In addition, Verisity will expand its existing toolkits and methods to enable complex verification environments to be packaged for designers leveraged as 'test writers'. The Hardware Designer Viewport will also include support for the appropriate designer verification extensions being defined by the IEEE 1364 working group and Accellera as part of SystemVerilog. Verisity is working with the industry to ensure that the Verilog standards converge to provide designers with a single, concise, easily adoptable and safe verification extension.
d) Software Engineers Viewport: will integrate the software engineering verification activities into the overall verification process with more optimized software module-level solutions and hardware-software chip-level solutions packaged into a more formalized Software Viewport. This viewport will support C/C++, register views and multiple links to varying types of software execution engines and debug views. Verisity already supports links to accept C/C++ code, and execute and debug the code on alternative platforms, including Mentor Graphic's Seamless hw/sw co-verification solution and host workstations.
e) Project Manager Viewport: will enable verification and project managers to track progress towards verification closure, and to collect statistics to help managers predict resources and verification timelines for current and future projects. This includes high-level views of all project metrics vs. the plan, convergence rates towards closure and a history of key metrics for each type of activity to better utilize resources -- both computing and human.
"Verification Viewports will allow each stakeholder to have their preferred view of advanced verification technology or pre-packaged environments for their unique needs," said Steve Glaser, vice president of corporate marketing and business development for Verisity. "Verisity has developed an extensive portfolio of solutions for the verification specialist, and will continue to expand its scope to meet the exponentially growing challenges of verifying complex designs. Over the next few years, Verisity will bring VPA to the hardware designers, software developers, verification specialists, architects and project managers who all have a strong stake in the verification process and must be linked together."
Verisity's strategy for Verification Viewports follows recent VPA product announcements of the System Verification Methodology (sVM) and Multi-channel generation for the chip/system level, and vManager for the project level. Verisity also recently announced a strategic collaboration with 0-In and Novas to define a complete nanometer verification process, supported by compatible flows and common data models. The Verification Viewports will further broaden the role of Verisity's VPA solutions by delivering the appropriate technology, methodology and expertise into different views optimized for each stakeholder in the verification process.
Verisity, Ltd. (NASDAQ: VRST), is the leading supplier of process automation solutions for the functional verification market. The company addresses customers' critical business issues with its market-leading software and intellectual property (IP) that effectively and efficiently verify the design of electronic systems and complex integrated circuits for the communications, computing, and consumer electronics global markets. Verisity's VPA solutions enable projects to move from executable verification plans to module, unit, and chip/system level 'total coverage' and verification closure, while maximizing productivity, product quality, and predictability of schedules. The company's strong market presence is driven by its proven technology, methodology and solid strategic partnerships and programs. Verisity's customer list includes leading companies in all strategic technology sectors. Verisity is a global organization with offices throughout Asia, Europe, and North America. Verisity's principal executive offices are located in Mountain View, California, with its principal research and development offices located in Rosh Ha'ain, Israel. For more information, visit www.verisity.com.
Verisity, the Verisity logo, Specman Elite and Verification Viewports are either registered trademarks or trademarks of Verisity Design, Inc. in the United States and/or other jurisdictions. All other trademarks are the property of their respective holders.
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