CoWare Helps MIPS Technologies Customers Optimize Processor Performance with CoWare ConvergenSC and the MIPS64 25KfT Core

CoWare Offers First Commercially Available MIPS64 Processor Support Package for SystemC Through its ConvergenSC Model Library

San Jose, CA., January 12, 2004 - CoWare® Inc., the leading supplier of system-level electronic design automation (EDA) software and services, and MIPS Technologies, Inc. (Nasdaq: MIPS) announced that the first SystemC-based processor support package (PSP) for the MIPS64 25KfT core has been added to CoWare's extensive ConvergenSCT Model Library. Together with CoWare's ConvergenSC system-level design solution, the PSP helps reduce overall design time for customers of MIPS Technologies by allowing them to explore and debug their designs at the system level.

"We are working closely with CoWare to produce SystemC-based models that provide the industry's best solution for our mutual customers' design needs," said Jack Browne, vice president of worldwide sales at MIPS Technologies. "This new offering from CoWare will help OEM customers who are using the 25Kf core to focus on product design without worrying about model integration. Toshiba is using the 25Kf core in their high-performance TX99 family, which is part of Toshiba's extensive MIPS-Based product line. With it Toshiba is offering its growing customer base the highest performance available for cost- and power-sensitive applications, such as automotive telematics, home gateway and office automation devices."

"We recently expanded our relationship with MIPS Technologies to include working closely together on development of models for new and future generations of its cores," said Mark Milligan, vice president of marketing, CoWare. "CoWare is committed to providing customers with the broadest range of IP models available. This new PSP is just the first of several MIPS-Based models that CoWare will release in the coming year. We are confident that customers can gain a competitive edge in the market by using this unique system-level solution."

The 25Kf core gives systems designers the highest performance available in licensable IP for 0.10 micron process technology and beyond, while offering low-power characteristics and low overall product cost. It meets the requirements of the most demanding embedded applications and is fully compatible with the MIPS32-bit architecture and cores, giving customers a seamless migration path to 64-bit processing.

By running simulations in the ConvergenSC environment together with the CoWare PSP for the 25Kf core, users can quickly determine the optimum architecture for their specific application and debug their software and hardware early in the design process. The new PSP is based on the MIPS MIPSsimT instruction set simulator (ISS), and is compatible with the MIPS Software Toolkit including the MIPS SDE software tool chain (compiler, assembler, linker) for the processor.

The PSP, in conjunction with CoWare's unique ConvergenSC analysis tools, lets customers pinpoint bottlenecks in their designs at the system level and iterate through various architectural options to reach the optimum solution, greatly speeding their time-to-market with the right product. The tools let customers perform detailed analysis of processor throughput and latency, as well as memory subsystem performance and bus analysis. They can then view the analysis results graphically and use that feedback to determine how they need to refine their design. With the ability to measure the key parameters that affect the performance of the processor in their design, users can design better performing systems.

Pricing and Availability

CoWare's PSP for the MIPS64 25Kf core will be available in production release in January 2004. Pricing starts at $10,000 (U.S.) for a one-year subscription license. CoWare's ConvergenSC is available now. ConvergenSC runs on Sun Solaris and Linux operating systems.

For the latest information and availability about this and other models in the ConvergenSC Model Library, contact John MacDermott, director, business development, at johnm@coware.com.

About MIPS Technologies

MIPS Technologies, Inc. is a leading provider of industry-standard processor architectures and cores for digital consumer and business applications. The company drives the broadest architectural alliance that is delivering 32- and 64-bit embedded RISC solutions. The company licenses its intellectual property to semiconductor companies, ASIC developers and system OEMs. MIPS Technologies and its licensees offer the widest range of robust, scalable processors in standard, custom, semi-custom and application-specific products. The company is based in Mountain View, Calif., and can be reached at +1 (650) 567-5000 or www.mips.com.

About CoWare

CoWare is the leading supplier of system-level electronic design automation (EDA) software tools and services. CoWare offers a comprehensive set of electronic system-level (ESL) tools that enable SoC developers to "differentiate by design" through the creation of system-IP including embedded processors, on-chip buses, and DSP algorithms; the architecture of optimized SoC platforms; and hardware/software co-design. The company's solutions are based on open industry standards including SystemC. CoWare's customers are major systems, semiconductor, and IP companies in the market where consumer electronics, computing, and communications converge. CoWare's corporate investors include ARM Ltd. [(LSE:ARM);(Nasdaq: ARMHY)], Cadence Design Systems (NYSE:CDN), ST Microelectronics (NYSE:STM), and Sony Corporation (NYSE:SNE). CoWare is headquartered in San Jose, Calif., and has offices around the world. For more information about CoWare and its products and services, visit http://www.coware.com.

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ConvergenSC is a trademark of CoWare, Inc. CoWare is a registered trademark of CoWare, Inc. in the United States. All other trademarks are the property of their respective owners.

MIPS is a registered trademark in the United States and other countries, and MIPS64 and MIPS-based are trademarks of MIPS Technologies, Inc. All other trademarks referred to herein are the property of their respective owners.

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